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asmicon/bankmachine: respect SDRAM write-to-precharge specification

This commit is contained in:
Sebastien Bourdeauducq 2012-08-04 22:49:43 +02:00
parent 1451cad710
commit ea4c214790
1 changed files with 20 additions and 4 deletions
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16
milkymist/asmicon/bankmachine.py
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@ -235,6 +235,19 @@ class BankMachine:
comb.append(self.cmd.tag.eq(cmdsource.tag)) comb.append(self.cmd.tag.eq(cmdsource.tag))
# Respect write-to-precharge specification
precharge_ok = Signal()
t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
unsafe_precharge_count = Signal(BV(bits_for(t_unsafe_precharge)))
comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
sync += [
If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
unsafe_precharge_count.eq(t_unsafe_precharge)
).Elif(~precharge_ok,
unsafe_precharge_count.eq(unsafe_precharge_count-1)
)
]
# Control and command generation FSM # Control and command generation FSM
fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[ fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
("TRP", "ACTIVATE", self.timing_settings.tRP-1), ("TRP", "ACTIVATE", self.timing_settings.tRP-1),
@ -246,6 +259,7 @@ class BankMachine:
).Elif(cmdsource.stb, ).Elif(cmdsource.stb,
If(has_openrow, If(has_openrow,
If(hit, If(hit,
# NB: write-to-read specification is enforced by multiplexer
self.cmd.stb.eq(1), self.cmd.stb.eq(1),
cmdsource.ack.eq(self.cmd.ack), cmdsource.ack.eq(self.cmd.ack),
self.cmd.is_read.eq(~cmdsource.we), self.cmd.is_read.eq(~cmdsource.we),
@ -265,11 +279,13 @@ class BankMachine:
# 1. we are presenting the column address, A10 is always low # 1. we are presenting the column address, A10 is always low
# 2. since we always go to the ACTIVATE state, we do not need # 2. since we always go to the ACTIVATE state, we do not need
# to assert track_close. # to assert track_close.
If(precharge_ok,
self.cmd.stb.eq(1), self.cmd.stb.eq(1),
If(self.cmd.ack, fsm.next_state(fsm.TRP)), If(self.cmd.ack, fsm.next_state(fsm.TRP)),
self.cmd.ras_n.eq(0), self.cmd.ras_n.eq(0),
self.cmd.we_n.eq(0) self.cmd.we_n.eq(0)
) )
)
fsm.act(fsm.ACTIVATE, fsm.act(fsm.ACTIVATE,
s_row_adr.eq(1), s_row_adr.eq(1),
track_open.eq(1), track_open.eq(1),