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README: update copyright year and make sure LICENSE/README both mention MiSoC

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Florent Kermarrec 2020-01-27 12:12:53 +01:00
parent 95cfa6a82c
commit ea5ef8c1be
3 changed files with 10 additions and 6 deletions
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8
LICENSE
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@ -1,6 +1,10 @@
LiteX is a MiSoC-based SoC builder using Migen as Python DSL. LiteX is a FPGA design/SoC builder that can be used to build cores, create
SoCs and full FPGA designs.
Unless otherwise noted, LiteX is copyright (C) 2012-2019 Enjoy-Digital. LiteX is based on Migen/MiSoC and provides specific building/debugging tools
for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Unless otherwise noted, LiteX is copyright (C) 2012-2020 Enjoy-Digital.
Unless otherwise noted, MiSoC is copyright (C) 2012-2015 Enjoy-Digital. Unless otherwise noted, MiSoC is copyright (C) 2012-2015 Enjoy-Digital.
Unless otherwise noted, MiSoC is copyright (C) 2007-2015 M-Labs Ltd. Unless otherwise noted, MiSoC is copyright (C) 2007-2015 M-Labs Ltd.
All rights reserved. All rights reserved.

6
README.md
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@ -1,6 +1,6 @@
![LiteX](https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png) ![LiteX](https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png)
``` ```
Copyright 2012-2019 / EnjoyDigital Copyright 2012-2020 / EnjoyDigital
``` ```
[![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex) [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg) ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
@ -8,8 +8,8 @@
LiteX is a FPGA design/SoC builder that can be used to build cores, create LiteX is a FPGA design/SoC builder that can be used to build cores, create
SoCs and full FPGA designs. SoCs and full FPGA designs.
LiteX is based on Migen and provides specific building/debugging tools for LiteX is based on Migen/MiSoC and provides specific building/debugging tools
a higher level of abstraction and compatibily with the LiteX core ecosystem. for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
SoC builder to create/develop/debug FPGA SoCs in Python. SoC builder to create/develop/debug FPGA SoCs in Python.

2
litex/soc/software/bios/main.c
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@ -567,7 +567,7 @@ int main(int i, char **c)
printf("\e[1m / /__/ / __/ -_)> <\e[0m\n"); printf("\e[1m / /__/ / __/ -_)> <\e[0m\n");
printf("\e[1m /____/_/\\__/\\__/_/|_|\e[0m\n"); printf("\e[1m /____/_/\\__/\\__/_/|_|\e[0m\n");
printf("\n"); printf("\n");
printf(" (c) Copyright 2012-2019 Enjoy-Digital\n"); printf(" (c) Copyright 2012-2020 Enjoy-Digital\n");
printf("\n"); printf("\n");
printf(" BIOS built on "__DATE__" "__TIME__"\n"); printf(" BIOS built on "__DATE__" "__TIME__"\n");
crcbios(); crcbios();