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litesata: update build core target generation

This commit is contained in:
Florent Kermarrec 2015-04-09 00:00:25 +02:00
parent 03aa972bb6
commit ea613cd8ee
2 changed files with 11 additions and 9 deletions
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11
misoclib/mem/litesata/example_designs/make.py
View File

@ -69,8 +69,11 @@ if __name__ == "__main__":
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs) soc = top_class(platform, **top_kwargs)
soc.finalize() soc.finalize()
memory_regions = soc.get_memory_regions() try:
csr_regions = soc.get_csr_regions() memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
except:
pass
# decode actions # decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"] action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@ -139,8 +142,8 @@ BIST: {}
MultiReg: XilinxMultiReg, MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
} }
src = verilog.convert(soc, ios, special_overrides=so) v_output = verilog.convert(soc, ios, special_overrides=so)
tools.write_to_file("build/litesata.v", src) v_output.write("build/litesata.v")
if actions["build-bitstream"]: if actions["build-bitstream"]:
vns = platform.build(soc, build_name=build_name, run=True) vns = platform.build(soc, build_name=build_name, run=True)

9
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
View File

@ -1,6 +1,5 @@
from mibuild.generic_platform import * from mibuild.generic_platform import *
from mibuild.xilinx.common import CRG_DS from mibuild.xilinx.platform import XilinxPlatform
from mibuild.xilinx.vivado import XilinxVivadoPlatform
_io = [ _io = [
("sys_clk", 0, Pins("X")), ("sys_clk", 0, Pins("X")),
@ -16,9 +15,9 @@ _io = [
), ),
] ]
class Platform(XilinxVivadoPlatform): class Platform(XilinxPlatform):
def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs): def __init__(self, device="xc7k325t", programmer=""):
XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory) XilinxPlatform.__init__(self, device, _io)
def do_finalize(self, *args, **kwargs): def do_finalize(self, *args, **kwargs):
pass pass