litesata: update build core target generation
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parent
03aa972bb6
commit
ea613cd8ee
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@ -69,8 +69,11 @@ if __name__ == "__main__":
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top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
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soc = top_class(platform, **top_kwargs)
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soc.finalize()
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try:
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memory_regions = soc.get_memory_regions()
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csr_regions = soc.get_csr_regions()
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except:
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pass
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# decode actions
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action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
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@ -139,8 +142,8 @@ BIST: {}
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MultiReg: XilinxMultiReg,
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
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}
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src = verilog.convert(soc, ios, special_overrides=so)
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tools.write_to_file("build/litesata.v", src)
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v_output = verilog.convert(soc, ios, special_overrides=so)
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v_output.write("build/litesata.v")
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if actions["build-bitstream"]:
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vns = platform.build(soc, build_name=build_name, run=True)
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@ -1,6 +1,5 @@
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from mibuild.generic_platform import *
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from mibuild.xilinx.common import CRG_DS
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from mibuild.xilinx.vivado import XilinxVivadoPlatform
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from mibuild.xilinx.platform import XilinxPlatform
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_io = [
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("sys_clk", 0, Pins("X")),
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@ -16,9 +15,9 @@ _io = [
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),
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]
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class Platform(XilinxVivadoPlatform):
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
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XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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class Platform(XilinxPlatform):
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def __init__(self, device="xc7k325t", programmer=""):
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XilinxPlatform.__init__(self, device, _io)
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def do_finalize(self, *args, **kwargs):
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pass
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