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cores/spi: rename add_control paramter to add_csr

This commit is contained in:
Florent Kermarrec 2019-07-20 12:54:45 +02:00
parent ec411a6ac1
commit ea619e3afe
2 changed files with 5 additions and 5 deletions
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8
litex/soc/cores/spi.py
View File

@ -21,7 +21,7 @@ class SPIMaster(Module, AutoCSR):
configurable data_width and frequency. configurable data_width and frequency.
""" """
pads_layout = [("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)] pads_layout = [("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)]
def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_control=True): def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True):
if pads is None: if pads is None:
pads = Record(self.pads_layout) pads = Record(self.pads_layout)
if not hasattr(pads, "cs_n"): if not hasattr(pads, "cs_n"):
@ -38,8 +38,8 @@ class SPIMaster(Module, AutoCSR):
self.cs = Signal(len(pads.cs_n), reset=1) self.cs = Signal(len(pads.cs_n), reset=1)
self.loopback = Signal() self.loopback = Signal()
if with_control: if with_csr:
self.add_control() self.add_csr()
# # # # # #
@ -127,7 +127,7 @@ class SPIMaster(Module, AutoCSR):
) )
) )
def add_control(self): def add_csr(self):
self._control = CSRStorage(16) self._control = CSRStorage(16)
self._status = CSRStatus() self._status = CSRStatus()
self._mosi = CSRStorage(self.data_width) self._mosi = CSRStorage(self.data_width)

2
test/test_spi.py
View File

@ -26,5 +26,5 @@ class TestSPI(unittest.TestCase):
yield yield
self.assertEqual((yield dut.miso), 0xdeadbeef) self.assertEqual((yield dut.miso), 0xdeadbeef)
dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_control=False) dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False)
run_simulation(dut, generator(dut)) run_simulation(dut, generator(dut))