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https://github.com/enjoy-digital/litex.git
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fhdl: support len() on all values
This commit is contained in:
Sebastien Bourdeauducq
parent
75d33a0c05
commit
ea63389823
3 changed files with 83 additions and 83 deletions
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@ -110,6 +110,9 @@ class Value(HUID):
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def eq(self, r):
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return _Assign(self, r)
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def __len__(self):
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return value_bits_sign(self)[0]
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def __hash__(self):
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return HUID.__hash__(self)
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@ -164,9 +167,6 @@ class Signal(Value):
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self.name_override = name_override
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self.backtrace = tracer.trace_back(name)
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def __len__(self): # TODO: remove (use tools.value_bits_sign instead)
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return self.nbits
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def __repr__(self):
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return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"
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@ -299,3 +299,81 @@ class Fragment:
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self.specials | other.specials,
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self.clock_domains + other.clock_domains,
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self.sim + other.sim)
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def value_bits_sign(v):
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if isinstance(v, bool):
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return 1, False
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elif isinstance(v, int):
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return bits_for(v), v < 0
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elif isinstance(v, Signal):
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return v.nbits, v.signed
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elif isinstance(v, (ClockSignal, ResetSignal)):
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return 1, False
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elif isinstance(v, _Operator):
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obs = list(map(value_bits_sign, v.operands))
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if v.op == "+" or v.op == "-":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]) + 1, False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]) + 1, True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]) + 1, True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1) + 1, True
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elif v.op == "*":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return obs[0][0] + obs[1][0]
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return obs[0][0] + obs[1][0] - 1
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else:
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# one operand signed, the other unsigned (add sign bit)
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return obs[0][0] + obs[1][0] + 1 - 1
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elif v.op == "<<<":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1) - 1
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else:
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extra = 2**obs[1][0] - 1
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return obs[0][0] + extra, obs[0][1]
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elif v.op == ">>>":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1)
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else:
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extra = 0
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return obs[0][0] + extra, obs[0][1]
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elif v.op == "&" or v.op == "^" or v.op == "|":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]), False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]), True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]), True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1), True
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elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
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or v.op == ">" or v.op == ">=":
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return 1, False
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elif v.op == "~":
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return obs[0]
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else:
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raise TypeError
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elif isinstance(v, _Slice):
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return v.stop - v.start, value_bits_sign(v.value)[1]
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elif isinstance(v, Cat):
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return sum(value_bits_sign(sv)[0] for sv in v.l), False
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elif isinstance(v, Replicate):
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return (value_bits_sign(v.v)[0])*v.n, False
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elif isinstance(v, _ArrayProxy):
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bsc = map(value_bits_sign, v.choices)
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return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
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else:
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raise TypeError
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@ -1,7 +1,7 @@
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import collections
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
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from migen.fhdl.structure import _Slice, _Assign
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from migen.fhdl.visit import NodeVisitor, NodeTransformer
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def bitreverse(s):
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@ -117,84 +117,6 @@ def insert_reset(rst, sl):
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resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
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return [If(rst, *resetcode).Else(*sl)]
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def value_bits_sign(v):
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if isinstance(v, bool):
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return 1, False
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elif isinstance(v, int):
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return bits_for(v), v < 0
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elif isinstance(v, Signal):
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return v.nbits, v.signed
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elif isinstance(v, (ClockSignal, ResetSignal)):
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return 1, False
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elif isinstance(v, _Operator):
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obs = list(map(value_bits_sign, v.operands))
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if v.op == "+" or v.op == "-":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]) + 1, False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]) + 1, True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]) + 1, True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1) + 1, True
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elif v.op == "*":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return obs[0][0] + obs[1][0]
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return obs[0][0] + obs[1][0] - 1
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else:
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# one operand signed, the other unsigned (add sign bit)
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return obs[0][0] + obs[1][0] + 1 - 1
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elif v.op == "<<<":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1) - 1
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else:
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extra = 2**obs[1][0] - 1
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return obs[0][0] + extra, obs[0][1]
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elif v.op == ">>>":
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if obs[1][1]:
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extra = 2**(obs[1][0] - 1)
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else:
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extra = 0
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return obs[0][0] + extra, obs[0][1]
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elif v.op == "&" or v.op == "^" or v.op == "|":
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if not obs[0][1] and not obs[1][1]:
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# both operands unsigned
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return max(obs[0][0], obs[1][0]), False
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elif obs[0][1] and obs[1][1]:
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# both operands signed
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return max(obs[0][0], obs[1][0]), True
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elif not obs[0][1] and obs[1][1]:
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# first operand unsigned (add sign bit), second operand signed
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return max(obs[0][0] + 1, obs[1][0]), True
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else:
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# first signed, second operand unsigned (add sign bit)
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return max(obs[0][0], obs[1][0] + 1), True
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elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
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or v.op == ">" or v.op == ">=":
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return 1, False
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elif v.op == "~":
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return obs[0]
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else:
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raise TypeError
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elif isinstance(v, _Slice):
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return v.stop - v.start, value_bits_sign(v.value)[1]
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elif isinstance(v, Cat):
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return sum(value_bits_sign(sv)[0] for sv in v.l), False
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elif isinstance(v, Replicate):
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return (value_bits_sign(v.v)[0])*v.n, False
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elif isinstance(v, _ArrayProxy):
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bsc = map(value_bits_sign, v.choices)
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return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
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else:
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raise TypeError
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# Basics are FHDL structure elements that back-ends are not required to support
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# but can be expressed in terms of other elements (lowered) before conversion.
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class _BasicLowerer(NodeTransformer):
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@ -1,6 +1,6 @@
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Special
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from migen.fhdl.tools import value_bits_sign, list_signals
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from migen.fhdl.tools import list_signals
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class MultiRegImpl:
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def __init__(self, i, o, odomain, n):
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