Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

litesata: pep8 (E225)

Browse source
This commit is contained in:
Florent Kermarrec 2015-04-13 15:44:04 +02:00
parent a9b42161c0
commit ea67080462
11 changed files with 26 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
misoclib/mem/litesata/core/link/cont.py
View file

@ -47,7 +47,7 @@ class LiteSATACONTInserter(Module):
Record.connect(sink, source),
If(sink.stb,
If(~change,
counter.ce.eq(sink.ack & (counter.value !=2)),
counter.ce.eq(sink.ack & (counter.value != 2)),
# insert CONT
If(counter.value == 1,
source.charisk.eq(0b0001),

10
misoclib/mem/litesata/example_designs/test/bist.py
View file

@ -30,7 +30,7 @@ class LiteSATABISTUnitDriver:
self.frequency = regs.identifier_frequency.read()
self.time = 0
for s in ["start", "sector", "count", "loops", "random", "done", "aborted", "errors", "cycles"]:
setattr(self, s, getattr(regs, name + "_"+ s))
setattr(self, s, getattr(regs, name + "_" + s))
def run(self, sector, count, loops, random, blocking=True, hw_timer=True):
self.sector.write(sector)
@ -73,7 +73,7 @@ class LiteSATABISTIdentifyDriver:
self.regs = regs
self.name = name
for s in ["start", "done", "source_stb", "source_ack", "source_data"]:
setattr(self, s, getattr(regs, name + "_identify_"+ s))
setattr(self, s, getattr(regs, name + "_identify_" + s))
self.data = []
def read_fifo(self):
@ -123,7 +123,7 @@ class LiteSATABISTIdentifyDriver:
info = "Serial Number: " + self.serial_number + "\n"
info += "Firmware Revision: " + self.firmware_revision + "\n"
info += "Model Number: " + self.model_number + "\n"
info += "Capacity: %3.2f GB\n" %((self.total_sectors*logical_sector_size)/GB)
info += "Capacity: {:3.2f} GB\n".format((self.total_sectors*logical_sector_size)/GB)
for k, v in self.capabilities.items():
info += k + ": " + str(v) + "\n"
print(info, end="")
@ -189,9 +189,9 @@ if __name__ == "__main__":
if not read_done:
retry += 1
print("sector=%d(%dMB) wr_speed=%4.2fMB/s rd_speed=%4.2fMB/s errors=%d retry=%d" %(
print("sector={:d}({:d}MB) wr_speed={:4.2f}MB/s rd_speed={:4.2f}MB/s errors={:d} retry={:d}".format(
sector,
run_sectors*logical_sector_size/MB,
run_sectors*logical_sector_size/MB,
write_speed/MB,
read_speed/MB,
write_errors + read_errors,

4
misoclib/mem/litesata/example_designs/test/tools.py
View file

@ -37,11 +37,11 @@ def link_trace(mila, tx_data_name, rx_data_name):
rx_data = var.values
for i in range(len(tx_data)):
tx = "%08x " %tx_data[i]
tx = "{:08x} ".format(tx_data[i])
tx += decode_primitive(tx_data[i])
tx += " "*(16-len(tx))
rx = "%08x " %rx_data[i]
rx = "{:08x} ".format(rx_data[i])
rx += decode_primitive(rx_data[i])
rx += " "*(16-len(rx))

2
misoclib/mem/litesata/test/command_tb.py
View file

@ -93,7 +93,7 @@ class TB(Module):
# check results
s, l, e = check(write_data, read_data)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)

2
misoclib/mem/litesata/test/common.py
View file

@ -24,7 +24,7 @@ def check(p1, p2):
else:
ref, res = p2, p1
shift = 0
while((ref[0] != res[0]) and (len(res)>1)):
while((ref[0] != res[0]) and (len(res) > 1)):
res.pop(0)
shift += 1
length = min(len(ref), len(res))

2
misoclib/mem/litesata/test/cont_tb.py
View file

@ -92,7 +92,7 @@ class TB(Module):
# check results
s, l, e = check(streamer_packet, self.logger.packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":

4
misoclib/mem/litesata/test/crc_tb.py
View file

@ -15,7 +15,7 @@ class TB(Module):
def get_c_crc(self, datas):
stdin = ""
for data in datas:
stdin += "0x%08x " %data
stdin += "0x{:08x} ".format(data)
stdin += "exit"
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
process.stdin.write(stdin.encode("ASCII"))
@ -52,7 +52,7 @@ class TB(Module):
# check results
s, l, e = check(c_crc, sim_crc)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
from migen.sim.generic import run_simulation

14
misoclib/mem/litesata/test/hdd.py
View file

@ -75,11 +75,11 @@ class PHYLayer(Module):
yield from self.rx.receive()
def __repr__(self):
receiving = "%08x " %self.rx.dword.dat
receiving = "{:08x} ".format(self.rx.dword.dat)
receiving += decode_primitive(self.rx.dword.dat)
receiving += " "*(16-len(receiving))
sending = "%08x " %self.tx.dword.dat
sending = "{:08x} ".format(self.tx.dword.dat)
sending += decode_primitive(self.tx.dword.dat)
sending += " "*(16-len(sending))
@ -115,7 +115,7 @@ class LinkRXPacket(LinkPacket):
def check_crc(self):
stdin = ""
for v in self[:-1]:
stdin += "0x%08x " %v
stdin += "0x{:08x} ".format(v)
stdin += "exit"
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
process.stdin.write(stdin.encode("ASCII"))
@ -134,7 +134,7 @@ class LinkTXPacket(LinkPacket):
def insert_crc(self):
stdin = ""
for v in self:
stdin += "0x%08x " %v
stdin += "0x{:08x} ".foramt(v)
stdin += "exit"
with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
process.stdin.write(stdin.encode("ASCII"))
@ -313,7 +313,7 @@ class FIS:
else:
r = "<<<<<<<<\n"
for k in sorted(self.description.keys()):
r += k + " : 0x%x" %getattr(self, k) + "\n"
r += k + " : 0x{:x}".format(getattr(self, k)) + "\n"
return r
@ -362,7 +362,7 @@ class FIS_DATA(FIS):
r = "FIS_DATA\n"
r += FIS.__repr__(self)
for data in self.packet[1:]:
r += "%08x\n" %data
r += "{:08x}\n".format(data)
return r
@ -377,7 +377,7 @@ class FIS_UNKNOWN(FIS):
else:
r += "<<<<<<<<\n"
for dword in self.packet:
r += "%08x\n" %dword
r += "{:08x}\n".format(dword)
return r

2
misoclib/mem/litesata/test/link_tb.py
View file

@ -44,7 +44,7 @@ class TB(Module):
# check results
s, l, e = check(streamer_packet, self.logger.packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":

6
misoclib/mem/litesata/test/phy_datapath_tb.py
View file

@ -81,13 +81,13 @@ class TB(Module):
yield from self.streamer.send(streamer_packet)
yield from self.logger.receive(512)
for d in self.logger.packet:
r = "%08x " %d
r +=decode_primitive(d)
r = "{:08x} ".format(d)
r += decode_primitive(d)
print(r)
# check results
#s, l, e = check(streamer_packet, self.logger.packet)
#print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
#print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":

4
misoclib/mem/litesata/test/scrambler_tb.py
View file

@ -12,7 +12,7 @@ class TB(Module):
self.length = length
def get_c_values(self, length):
stdin = "0x%08x" %length
stdin = "0x{:08x}".format(length)
with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
process.stdin.write(stdin.encode("ASCII"))
out, err = process.communicate()
@ -42,7 +42,7 @@ class TB(Module):
# check results
s, l, e = check(c_values, sim_values)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
from migen.sim.generic import run_simulation