test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.

This commit is contained in:
Florent Kermarrec 2022-01-25 10:49:33 +01:00
parent 6ff8b6e4ed
commit ea6bb3dd80
2 changed files with 18 additions and 15 deletions
litex/soc/cores/clock
test

View file

@ -12,7 +12,7 @@ from litex.soc.cores.clock.intel_cyclone10 import Cyclone10LPPLL
# Lattice
from litex.soc.cores.clock.lattice_ice40 import iCE40PLL
from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL
from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL, ECP5Delay
from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
# Efinix

View file

@ -13,14 +13,14 @@ from litex.soc.cores.clock import *
class TestClock(unittest.TestCase):
# Xilinx / Spartan 6
def test_s6pll(self):
def test_s6_pll(self):
pll = S6PLL()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
pll.compute_config()
def test_s6dcm(self):
def test_s6_dcm(self):
dcm = S6DCM()
dcm.register_clkin(Signal(), 100e6)
for i in range(dcm.nclkouts_max):
@ -28,14 +28,14 @@ class TestClock(unittest.TestCase):
dcm.compute_config()
# Xilinx / 7-Series
def test_s7pll(self):
def test_s7_pll(self):
pll = S7PLL()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
pll.compute_config()
def test_s7mmcm(self):
def test_s7_mmcm(self):
mmcm = S7MMCM()
mmcm.register_clkin(Signal(), 100e6)
for i in range(mmcm.nclkouts_max):
@ -43,14 +43,14 @@ class TestClock(unittest.TestCase):
mmcm.compute_config()
# Xilinx / Ultrascale
def test_uspll(self):
def test_us_pll(self):
pll = USPLL()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
pll.compute_config()
def test_usmmcm(self):
def test_us_mmcm(self):
mmcm = USMMCM()
mmcm.register_clkin(Signal(), 100e6)
for i in range(mmcm.nclkouts_max):
@ -58,14 +58,14 @@ class TestClock(unittest.TestCase):
mmcm.compute_config()
# Xilinx / Ultrascale Plus
def test_usppll(self):
def test_us_ppll(self):
pll = USPPLL()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max):
pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
pll.compute_config()
def test_uspmmcm(self):
def test_us_pmmcm(self):
mmcm = USPMMCM()
mmcm.register_clkin(Signal(), 100e6)
for i in range(mmcm.nclkouts_max):
@ -73,7 +73,7 @@ class TestClock(unittest.TestCase):
mmcm.compute_config()
# Intel / CycloneIV
def test_cycloneivpll(self):
def test_cycloneiv_pll(self):
pll = CycloneIVPLL()
pll.register_clkin(Signal(), 50e6)
for i in range(pll.nclkouts_max):
@ -81,7 +81,7 @@ class TestClock(unittest.TestCase):
pll.compute_config()
# Intel / CycloneV
def test_cyclonevpll(self):
def test_cyclonev_pll(self):
pll = CycloneVPLL()
pll.register_clkin(Signal(), 50e6)
for i in range(pll.nclkouts_max):
@ -89,7 +89,7 @@ class TestClock(unittest.TestCase):
pll.compute_config()
# Intel / Cyclone10
def test_cyclone10pll(self):
def test_cyclone10_pll(self):
pll = Cyclone10LPPLL()
pll.register_clkin(Signal(), 50e6)
for i in range(pll.nclkouts_max):
@ -97,7 +97,7 @@ class TestClock(unittest.TestCase):
pll.compute_config()
# Intel / Max10
def test_max10pll(self):
def test_max10_pll(self):
pll = Max10PLL()
pll.register_clkin(Signal(), 50e6)
for i in range(pll.nclkouts_max):
@ -105,7 +105,7 @@ class TestClock(unittest.TestCase):
pll.compute_config()
# Lattice / iCE40
def test_ice40pll(self):
def test_ice40_pll(self):
pll = USMMCM()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max):
@ -113,7 +113,7 @@ class TestClock(unittest.TestCase):
pll.compute_config()
# Lattice / ECP5
def test_ecp5pll(self):
def test_ecp5_pll(self):
pll = ECP5PLL()
pll.register_clkin(Signal(), 100e6)
for i in range(pll.nclkouts_max-1):
@ -130,6 +130,9 @@ class TestClock(unittest.TestCase):
pll.create_clkout(ClockDomain("clkout4"), 175e6)
pll.compute_config()
def test_ecp5_delay(self):
delay = ECP5Delay()
# Lattice / NX
def test_nxpll(self):
pll = NXPLL()