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test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.
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2 changed files with 18 additions and 15 deletions
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@ -12,7 +12,7 @@ from litex.soc.cores.clock.intel_cyclone10 import Cyclone10LPPLL
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# Lattice
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from litex.soc.cores.clock.lattice_ice40 import iCE40PLL
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from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL
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from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL, ECP5Delay
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from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
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# Efinix
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@ -13,14 +13,14 @@ from litex.soc.cores.clock import *
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class TestClock(unittest.TestCase):
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# Xilinx / Spartan 6
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def test_s6pll(self):
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def test_s6_pll(self):
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pll = S6PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_s6dcm(self):
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def test_s6_dcm(self):
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dcm = S6DCM()
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dcm.register_clkin(Signal(), 100e6)
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for i in range(dcm.nclkouts_max):
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@ -28,14 +28,14 @@ class TestClock(unittest.TestCase):
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dcm.compute_config()
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# Xilinx / 7-Series
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def test_s7pll(self):
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def test_s7_pll(self):
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pll = S7PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_s7mmcm(self):
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def test_s7_mmcm(self):
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mmcm = S7MMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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@ -43,14 +43,14 @@ class TestClock(unittest.TestCase):
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mmcm.compute_config()
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# Xilinx / Ultrascale
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def test_uspll(self):
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def test_us_pll(self):
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pll = USPLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_usmmcm(self):
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def test_us_mmcm(self):
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mmcm = USMMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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@ -58,14 +58,14 @@ class TestClock(unittest.TestCase):
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mmcm.compute_config()
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# Xilinx / Ultrascale Plus
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def test_usppll(self):
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def test_us_ppll(self):
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pll = USPPLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_uspmmcm(self):
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def test_us_pmmcm(self):
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mmcm = USPMMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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@ -73,7 +73,7 @@ class TestClock(unittest.TestCase):
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mmcm.compute_config()
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# Intel / CycloneIV
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def test_cycloneivpll(self):
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def test_cycloneiv_pll(self):
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pll = CycloneIVPLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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@ -81,7 +81,7 @@ class TestClock(unittest.TestCase):
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pll.compute_config()
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# Intel / CycloneV
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def test_cyclonevpll(self):
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def test_cyclonev_pll(self):
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pll = CycloneVPLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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@ -89,7 +89,7 @@ class TestClock(unittest.TestCase):
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pll.compute_config()
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# Intel / Cyclone10
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def test_cyclone10pll(self):
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def test_cyclone10_pll(self):
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pll = Cyclone10LPPLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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@ -97,7 +97,7 @@ class TestClock(unittest.TestCase):
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pll.compute_config()
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# Intel / Max10
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def test_max10pll(self):
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def test_max10_pll(self):
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pll = Max10PLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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@ -105,7 +105,7 @@ class TestClock(unittest.TestCase):
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pll.compute_config()
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# Lattice / iCE40
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def test_ice40pll(self):
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def test_ice40_pll(self):
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pll = USMMCM()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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@ -113,7 +113,7 @@ class TestClock(unittest.TestCase):
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pll.compute_config()
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# Lattice / ECP5
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def test_ecp5pll(self):
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def test_ecp5_pll(self):
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pll = ECP5PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max-1):
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@ -130,6 +130,9 @@ class TestClock(unittest.TestCase):
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pll.create_clkout(ClockDomain("clkout4"), 175e6)
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pll.compute_config()
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def test_ecp5_delay(self):
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delay = ECP5Delay()
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# Lattice / NX
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def test_nxpll(self):
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pll = NXPLL()
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