cores/spi/spi_bone: Cosmetic cleanup pass (and remove unreachable ValueErrors).
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@ -11,6 +11,8 @@ from migen.genlib.cdc import MultiReg
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from litex.soc.integration.doc import ModuleDoc, AutoDoc
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from litex.soc.interconnect import wishbone, stream
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# SPIBone Doc for 4, 3 and 2 wires modes ----------------------------------------------------------
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class SPI4WireDocumentation(ModuleDoc):
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"""4-Wire SPI Protocol
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@ -112,6 +114,8 @@ class SPI2WireDocumentation(ModuleDoc):
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]}
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"""
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# SPIBone Core -------------------------------------------------------------------------------------
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class SPIBone(Module, ModuleDoc, AutoDoc):
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"""Wishbone Bridge over SPI
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@ -129,14 +133,25 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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self.wishbone = wishbone.Interface()
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# # #
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self.__doc__ = self.__doc__.format(wires)
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if wires == 4:
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self.mod_doc = SPI4WireDocumentation()
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elif wires == 3:
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self.mod_doc = SPI3WireDocumentation()
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elif wires == 2:
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self.mod_doc = SPI2WireDocumentation()
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# Parameters.
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# -----------
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if wires not in [2, 3, 4]:
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raise ValueError("`wires` must be 2, 3, or 4")
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# Doc.
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# ----
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self.__doc__ = self.__doc__.format(wires)
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self.mod_doc = {
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4 : SPI4WireDocumentation(),
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3 : SPI3WireDocumentation(),
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2 : SPI2WireDocumentation(),
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}[wires]
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# Signals.
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# --------
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clk = Signal()
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cs_n = Signal()
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mosi = Signal()
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@ -151,31 +166,27 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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wr = Signal()
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sync_byte = Signal(8)
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self.specials += [
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MultiReg(pads.clk, clk),
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]
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self.specials += MultiReg(pads.clk, clk)
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if wires == 2:
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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elif wires == 3:
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if wires == 3:
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self.specials += MultiReg(pads.cs_n, cs_n),
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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elif wires == 4:
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if wires == 4:
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self.specials += MultiReg(pads.cs_n, cs_n),
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self.specials += MultiReg(pads.mosi, mosi)
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if with_tristate:
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self.specials += Tristate(pads.miso, miso, ~cs_n)
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else:
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self.comb += pads.miso.eq(miso)
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else:
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raise ValueError("`wires` must be 2, 3, or 4")
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clk_last = Signal()
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clk_rising = Signal()
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@ -189,18 +200,17 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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self.submodules += fsm
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self.comb += fsm.reset.eq(cs_n)
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# Connect the Wishbone bus up to our values
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# Connect the Wishbone bus up to our values.
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self.comb += [
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self.wishbone.adr.eq(address[2:]),
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self.wishbone.dat_w.eq(value),
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self.wishbone.sel.eq(2**len(self.wishbone.sel) - 1)
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]
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# Constantly have the counter increase, except when it's reset
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# in the IDLE state
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# Constantly have the counter increase, except when it's reset in the IDLE state.
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self.sync += If(cs_n, counter.eq(0)).Elif(clk_rising, counter.eq(counter + 1))
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if wires == 2:
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if wires in [2]:
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fsm.act("IDLE",
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miso_en.eq(0),
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NextValue(miso, 1),
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@ -213,17 +223,15 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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NextValue(command, mosi),
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)
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)
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elif wires == 3 or wires == 4:
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if wires in [3, 4]:
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fsm.act("IDLE",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(clk_rising,
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NextState("GET_TYPE_BYTE"),
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NextValue(command, mosi),
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),
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)
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else:
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raise ValueError("invalid `wires` count: {}".format(wires))
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)
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# Determine if it's a read or a write
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fsm.act("GET_TYPE_BYTE",
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@ -343,15 +351,13 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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),
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)
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if wires == 3 or wires == 4:
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fsm.act("END",
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miso_en.eq(1),
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)
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elif wires == 2:
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if wires in [2]:
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fsm.act("END",
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miso_en.eq(0),
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NextValue(sync_byte, 0),
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NextState("IDLE")
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)
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else:
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raise ValueError("invalid `wires` count: {}".format(wires))
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if wires in [3, 4]:
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fsm.act("END",
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miso_en.eq(1),
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)
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