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transform/unroll: support for variables
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parent
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commit
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2 changed files with 26 additions and 10 deletions
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@ -4,16 +4,20 @@ from migen.fhdl import verilog
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x = Signal(BV(4))
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y = Signal(BV(4))
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acc = Signal(BV(4))
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acc = Signal(BV(4), variable=True)
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z = Signal()
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sync = [
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acc.eq(acc + x + y)
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If(acc == 2, acc.eq(3)),
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acc.eq(acc + x + y),
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z.eq(acc == 0)
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]
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n = 5
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xs = [Signal(BV(4)) for i in range(n)]
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ys = [Signal(BV(4)) for i in range(n)]
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accs = [Signal(BV(4)) for i in range(n)]
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zs = [Signal() for i in range(n)]
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sync_u = unroll_sync(sync, {x: xs, y: ys}, {acc: accs})
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print(verilog.convert(Fragment(sync=sync_u), ios=set(xs+ys+accs)))
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sync_u = unroll_sync(sync, {x: xs, y: ys}, {acc: accs, z: zs})
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print(verilog.convert(Fragment(sync=sync_u), ios=set(xs+ys+zs)))
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@ -80,15 +80,27 @@ def _variable_for(s, n):
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def unroll_sync(sync, inputs, outputs):
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sd_in = _list_step_dicts(inputs)
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sd_out = _list_step_dicts(outputs)
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do_var_old = sd_out[-1]
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r = []
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io_var_dict = sd_out[-1].copy()
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for n, (di, do) in enumerate(zip(sd_in, sd_out)):
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do_var = dict((k, _variable_for(v, n)) for k, v in do.items())
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di_plus_do_var_old = di.copy()
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di_plus_do_var_old.update(do_var_old)
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r += _replace(sync, di_plus_do_var_old, do_var)
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# initialize variables
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for k, v in io_var_dict.items():
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if k.variable:
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r.append(do_var[k].eq(io_var_dict[k]))
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io_var_dict[k] = do_var[k]
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# replace signals with intermediate variables and copy statements
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io_var_dict.update(di)
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r += _replace(sync, io_var_dict, do_var)
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# assign to output signals
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r += [v.eq(do_var[k]) for k, v in do.items()]
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do_var_old = do_var
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# prepare the next i+o dictionary
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io_var_dict = do_var.copy()
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return r
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