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Currently using a lite or minimal Vexriscv config with debug and breakpoints throws an error. Updated the GCC_FLAGS to include these two variants as well.

This commit is contained in:
riktw 2023-07-11 16:16:51 +02:00
parent 26732f626f
commit eb1afbad47
1 changed files with 26 additions and 24 deletions
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50
litex/soc/cores/cpu/vexriscv/core.py
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@ -50,30 +50,32 @@ CPU_VARIANTS = {
# GCC Flags ---------------------------------------------------------------------------------------- # GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = { GCC_FLAGS = {
# /---------- Base ISA # /---------- Base ISA
# | /----- Hardware Multiply + Divide # | /----- Hardware Multiply + Divide
# | |/---- Atomics # | |/---- Atomics
# | ||/--- Compressed ISA # | ||/--- Compressed ISA
# | |||/-- Single-Precision Floating-Point # | |||/-- Single-Precision Floating-Point
# | ||||/- Double-Precision Floating-Point # | ||||/- Double-Precision Floating-Point
# i macfd # i macfd
"minimal": "-march=rv32i2p0 -mabi=ilp32", "minimal": "-march=rv32i2p0 -mabi=ilp32",
"minimal+debug": "-march=rv32i2p0 -mabi=ilp32", "minimal+debug": "-march=rv32i2p0 -mabi=ilp32",
"lite": "-march=rv32i2p0_m -mabi=ilp32", "minimal+debug+hwbp": "-march=rv32i2p0 -mabi=ilp32",
"lite+debug": "-march=rv32i2p0_m -mabi=ilp32", "lite": "-march=rv32i2p0_m -mabi=ilp32",
"standard": "-march=rv32i2p0_m -mabi=ilp32", "lite+debug": "-march=rv32i2p0_m -mabi=ilp32",
"standard+debug": "-march=rv32i2p0_m -mabi=ilp32", "lite+debug+hwbp": "-march=rv32i2p0_m -mabi=ilp32",
"imac": "-march=rv32i2p0_mac -mabi=ilp32", "standard": "-march=rv32i2p0_m -mabi=ilp32",
"imac+debug": "-march=rv32i2p0_mac -mabi=ilp32", "standard+debug": "-march=rv32i2p0_m -mabi=ilp32",
"full": "-march=rv32i2p0_m -mabi=ilp32", "imac": "-march=rv32i2p0_mac -mabi=ilp32",
"full+cfu": "-march=rv32i2p0_m -mabi=ilp32", "imac+debug": "-march=rv32i2p0_mac -mabi=ilp32",
"full+debug": "-march=rv32i2p0_m -mabi=ilp32", "full": "-march=rv32i2p0_m -mabi=ilp32",
"full+cfu+debug": "-march=rv32i2p0_m -mabi=ilp32", "full+cfu": "-march=rv32i2p0_m -mabi=ilp32",
"linux": "-march=rv32i2p0_ma -mabi=ilp32", "full+debug": "-march=rv32i2p0_m -mabi=ilp32",
"linux+debug": "-march=rv32i2p0_ma -mabi=ilp32", "full+cfu+debug": "-march=rv32i2p0_m -mabi=ilp32",
"linux+no-dsp": "-march=rv32i2p0_ma -mabi=ilp32", "linux": "-march=rv32i2p0_ma -mabi=ilp32",
"secure": "-march=rv32i2p0_ma -mabi=ilp32", "linux+debug": "-march=rv32i2p0_ma -mabi=ilp32",
"secure+debug": "-march=rv32i2p0_ma -mabi=ilp32", "linux+no-dsp": "-march=rv32i2p0_ma -mabi=ilp32",
"secure": "-march=rv32i2p0_ma -mabi=ilp32",
"secure+debug": "-march=rv32i2p0_ma -mabi=ilp32",
} }
# VexRiscv Timer ----------------------------------------------------------------------------------- # VexRiscv Timer -----------------------------------------------------------------------------------