tools/litex_sim: cleanup/update (no functional change)
This commit is contained in:
Florent Kermarrec
parent
4798d6b750
commit
eb3888f68e
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@ -30,23 +30,23 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
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from litescope import LiteScopeAnalyzer
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# IOs ----------------------------------------------------------------------------------------------
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class SimPins(Pins):
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def __init__(self, n=1):
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Pins.__init__(self, "s "*n)
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_io = [
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("sys_clk", 0, SimPins(1)),
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("sys_rst", 0, SimPins(1)),
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("serial", 0,
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Subsignal("source_valid", SimPins()),
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Subsignal("source_ready", SimPins()),
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Subsignal("source_data", SimPins(8)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 0,
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Subsignal("none", SimPins()),
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@ -54,11 +54,11 @@ _io = [
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("eth", 0,
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Subsignal("source_valid", SimPins()),
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Subsignal("source_ready", SimPins()),
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Subsignal("source_data", SimPins(8)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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),
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("eth_clocks", 1,
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Subsignal("none", SimPins()),
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@ -66,14 +66,15 @@ _io = [
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("eth", 1,
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Subsignal("source_valid", SimPins()),
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Subsignal("source_ready", SimPins()),
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Subsignal("source_data", SimPins(8)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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Subsignal("sink_valid", SimPins()),
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Subsignal("sink_ready", SimPins()),
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Subsignal("sink_data", SimPins(8)),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(SimPlatform):
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default_clk_name = "sys_clk"
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@ -85,6 +86,7 @@ class Platform(SimPlatform):
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def do_finalize(self, fragment):
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pass
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# Simulation SoC -----------------------------------------------------------------------------------
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class SimSoC(SoCSDRAM):
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mem_map = {
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@ -93,86 +95,91 @@ class SimSoC(SoCSDRAM):
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mem_map.update(SoCSDRAM.mem_map)
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def __init__(self,
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with_sdram=False,
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with_ethernet=False,
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with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
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with_analyzer=False,
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with_sdram = False,
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with_ethernet = False,
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with_etherbone = False,
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etherbone_mac_address = 0x10e2d5000000,
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etherbone_ip_address = "192.168.1.50",
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with_analyzer = False,
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**kwargs):
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platform = Platform()
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platform = Platform()
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sys_clk_freq = int(1e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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ident="LiteX Simulation", ident_version=True,
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with_uart=False,
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integrated_rom_size = 0x8000,
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ident = "LiteX Simulation", ident_version=True,
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with_uart = False,
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**kwargs)
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# crg
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"))
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# serial
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# Serial -----------------------------------------------------------------------------------
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self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
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self.submodules.uart = uart.UART(self.uart_phy)
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self.add_csr("uart")
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self.add_interrupt("uart")
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# sdram
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# SDRAM ------------------------------------------------------------------------------------
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if with_sdram:
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sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings
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phy_settings = PhySettings(
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memtype="SDR",
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databits=32,
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dfi_databits=16,
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nphases=1,
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rdphase=0,
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wrphase=0,
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rdcmdphase=0,
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wrcmdphase=0,
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cl=2,
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read_latency=4,
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write_latency=0
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memtype = "SDR",
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databits = 32,
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dfi_databits = 16,
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nphases = 1,
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rdphase = 0,
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wrphase = 0,
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rdcmdphase = 0,
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wrcmdphase = 0,
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cl = 2,
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read_latency = 4,
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write_latency = 0
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)
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self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
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self.register_sdram(
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self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# reduce memtest size for simulation speedup
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# Reduce memtest size for simulation speedup
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self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
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self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
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assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces
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# ethernet
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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# eth phy
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# Ethernet PHY
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self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
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self.add_csr("ethphy")
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# eth mac
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# Ethernet MAC
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ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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interface = "wishbone",
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endianness = self.cpu.endianness)
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if with_etherbone:
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ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
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self.submodules.ethmac = ethmac
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# etherbone
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# Ethernet ---------------------------------------------------------------------------------
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if with_etherbone:
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# eth phy
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# Ethernet PHY
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self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
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self.add_csr("etherbonephy")
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# eth core
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# Ethernet MAC
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etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
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etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq)
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if with_ethernet:
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etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore)
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mac_address = etherbone_mac_address,
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ip_address = etherbone_ip_address,
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clk_freq = sys_clk_freq)
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self.submodules.etherbonecore = etherbonecore
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# etherbone
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# Etherbone
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self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master")
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self.add_wb_master(self.etherbone.wishbone.bus)
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# analyzer
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# Analyzer ---------------------------------------------------------------------------------
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if with_analyzer:
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analyzer_signals = [
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# FIXME: find interesting signals to probe
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@ -182,6 +189,7 @@ class SimSoC(SoCSDRAM):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
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self.add_csr("analyzer")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
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@ -217,6 +225,8 @@ def main():
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config.add_module("serial2console", "serial")
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# Configuration --------------------------------------------------------------------------------
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cpu_endianness = "little"
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if "cpu_type" in soc_kwargs:
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if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
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@ -236,14 +246,18 @@ def main():
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if args.with_etherbone:
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sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"})
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# SoC ------------------------------------------------------------------------------------------
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soc = SimSoC(
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with_sdram=args.with_sdram,
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with_ethernet=args.with_ethernet,
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with_etherbone=args.with_etherbone,
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with_analyzer=args.with_analyzer,
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with_sdram = args.with_sdram,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_analyzer = args.with_analyzer,
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**soc_kwargs)
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if args.ram_init is not None:
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soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
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# Build/Run ------------------------------------------------------------------------------------
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builder_kwargs["csr_csv"] = "csr.csv"
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builder = Builder(soc, **builder_kwargs)
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vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
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