bus/csr/SRAM: better handling of writes to memories larger than the CSR width
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@ -58,13 +58,9 @@ class SRAM(Module):
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mem = mem_or_size
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else:
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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if mem.width > data_width:
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = bits_for(csrw_per_memw-1)
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else:
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csrw_per_memw = 1
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word_bits = 0
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page_bits = _compute_page_bits(mem.depth + word_bits)
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int(mem.depth*csrw_per_memw, False)
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if page_bits:
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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else:
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@ -80,8 +76,7 @@ class SRAM(Module):
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###
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port = mem.get_port(write_capable=not read_only,
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we_granularity=data_width if not read_only and word_bits else 0)
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port = mem.get_port(write_capable=not read_only)
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self.specials += mem, port
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sel = Signal()
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@ -100,9 +95,15 @@ class SRAM(Module):
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)
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]
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if not read_only:
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wregs = []
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for i in range(csrw_per_memw-1):
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wreg = Signal(data_width)
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self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
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wregs.append(wreg)
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memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
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self.comb += [
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If(sel & self.bus.we, port.we.eq((1 << word_bits) >> self.bus.adr[:self.word_bits])),
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port.dat_w.eq(Replicate(self.bus.dat_w, csrw_per_memw))
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port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
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port.dat_w.eq(Cat(*memword_chunks))
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]
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else:
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self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
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