Merge pull request #502 from shuffle2/master
diamond: project generation improvements
This commit is contained in:
commit
ebcf67c10f
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@ -4,6 +4,7 @@
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# License: BSD
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import os
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import re
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import sys
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import subprocess
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import shutil
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@ -40,18 +41,29 @@ def _format_lpf(signame, pin, others, resname):
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return "\n".join(lpf)
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def _build_lpf(named_sc, named_pc, build_name):
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def _build_lpf(named_sc, named_pc, cc, build_name):
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lpf = []
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lpf.append("BLOCK RESETPATHS;")
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lpf.append("BLOCK ASYNCPATHS;")
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clk_ports = set()
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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lpf.append(_format_lpf(sig + "[" + str(i) + "]", p, others, resname))
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else:
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lpf.append(_format_lpf(sig, pins[0], others, resname))
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if sig in cc.keys():
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clk_ports.add(sig)
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if named_pc:
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lpf.append("\n\n".join(named_pc))
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lpf.append("\n".join(named_pc))
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# NOTE: The lpf is only used post-synthesis. Currently Synplify is fed no constraints,
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# so defaults to inferring clocks and trying to hit 200MHz on all of them.
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# NOTE: For additional options (PAR_ADJ, etc), use add_platform_command
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for clk, freq in cc.items():
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sig_type = "PORT" if clk in clk_ports else "NET"
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lpf.append("FREQUENCY {} \"{}\" {} MHz;".format(sig_type, clk, freq))
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tools.write_to_file(build_name + ".lpf", "\n".join(lpf))
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# Project (.tcl) -----------------------------------------------------------------------------------
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@ -67,13 +79,15 @@ def _build_tcl(device, sources, vincpaths, build_name):
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"-synthesis \"synplify\""
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]))
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def tcl_path(path): return path.replace("\\", "/")
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# Add include paths
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vincpath = ';'.join(map(lambda x: x.replace('\\', '/'), vincpaths))
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vincpath = ";".join(map(lambda x: tcl_path(x), vincpaths))
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tcl.append("prj_impl option {include path} {\"" + vincpath + "\"}")
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# Add sources
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for filename, language, library in sources:
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tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\" -work " + library)
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tcl.append("prj_src add \"{}\" -work {}".format(tcl_path(filename), library))
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# Set top level
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tcl.append("prj_impl option top \"{}\"".format(build_name))
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@ -89,6 +103,10 @@ def _build_tcl(device, sources, vincpaths, build_name):
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tcl.append("prj_run Export -impl impl -task Bitgen")
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if _produces_jedec(device):
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tcl.append("prj_run Export -impl impl -task Jedecgen")
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# Cleanly close the project
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tcl.append("prj_project close")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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# Script -------------------------------------------------------------------------------------------
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@ -130,6 +148,35 @@ def _run_script(script):
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if subprocess.call(shell + [script]) != 0:
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raise OSError("Subprocess failed")
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# This operates the same way tmcheck does, but tmcheck isn't usable without gui
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def _check_timing(build_name):
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lines = open("impl/{}_impl.par".format(build_name), "r").readlines()
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runs = [None, None]
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for i in range(len(lines)-1):
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if lines[i].startswith("Level/") and lines[i+1].startswith("Cost "):
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runs[0] = i + 2
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if lines[i].startswith("* : Design saved.") and runs[0] is not None:
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runs[1] = i
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break
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assert all(map(lambda x: x is not None, runs))
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p = re.compile(r"(^\s*\S+\s+\*?\s+[0-9]+\s+)(\S+)(\s+\S+\s+)(\S+)(\s+.*)")
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for l in lines[runs[0]:runs[1]]:
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m = p.match(l)
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if m is None: continue
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limit = 1e-8
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setup = m.group(2)
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hold = m.group(4)
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# if there were no freq constraints in lpf, ratings will be dashed.
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# results will likely be terribly unreliable, so bail
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assert not setup == hold == "-", "No timing constraints were provided"
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setup, hold = map(float, (setup, hold))
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if setup > limit and hold > limit:
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# at least one run met timing
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# XXX is this necessarily the run from which outputs will be used?
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return
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raise Exception("Failed to meet timing")
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# LatticeDiamondToolchain --------------------------------------------------------------------------
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class LatticeDiamondToolchain:
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@ -149,12 +196,14 @@ class LatticeDiamondToolchain:
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special_overrides = common.lattice_ecp5_special_overrides
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def __init__(self):
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self.period_constraints = []
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self.false_paths = set() # FIXME: use it
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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timingstrict = True,
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**kwargs):
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# Create build directory
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@ -174,8 +223,15 @@ class LatticeDiamondToolchain:
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v_output.write(v_file)
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platform.add_source(v_file)
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cc = {}
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for (clk, freq) in self.period_constraints:
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clk_name = v_output.ns.get_name(clk)
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if clk_name in cc and cc[clk_name] != freq:
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raise ConstraintError("Differing period constraints on {}".format(clk_name))
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cc[clk_name] = freq
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# Generate design constraints file (.lpf)
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_build_lpf(named_sc, named_pc, build_name)
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_build_lpf(named_sc, named_pc, cc, build_name)
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# Generate design script file (.tcl)
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_build_tcl(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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@ -186,16 +242,18 @@ class LatticeDiamondToolchain:
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# Run
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if run:
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_run_script(script)
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if timingstrict:
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_check_timing(build_name)
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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# TODO: handle differential clk
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platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(
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freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
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clk.attr.add("keep")
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freq = str(float(1/period)*1000)
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self.period_constraints.append((clk, freq))
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def add_false_path_constraint(self, platform, from_, to):
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from_.attr.add("keep")
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