transport: simplify tx and reduce ressource usage
This commit is contained in:
Florent Kermarrec
parent
1b20831541
commit
ebf1faed5b
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@ -33,36 +33,37 @@ class LiteSATACommandTX(Module):
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self.dwords_counter = dwords_counter = Counter(max=fis_max_dwords)
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identify = Signal()
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is_write = Signal()
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is_read = Signal()
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is_identify = Signal()
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(0),
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If(sink.stb & sink.sop,
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If(sink.write,
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NextState("SEND_WRITE_DMA_CMD")
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).Elif(sink.read,
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NextState("SEND_READ_DMA_OR_IDENTIFY_CMD")
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).Else(
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sink.ack.eq(1)
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)
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NextState("SEND_CMD")
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).Else(
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sink.ack.eq(1)
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)
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(sink.identify)
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is_write.eq(sink.write),
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is_read.eq(sink.read),
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is_identify.eq(sink.identify),
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)
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fsm.act("SEND_WRITE_DMA_CMD",
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fsm.act("SEND_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["WRITE_DMA_EXT"]),
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If(sink.stb & transport.sink.ack,
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NextState("WAIT_DMA_ACTIVATE")
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If(transport.sink.stb & transport.sink.ack,
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If(is_write,
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NextState("WAIT_DMA_ACTIVATE")
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).Else(
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NextState("IDLE")
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)
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)
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)
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fsm.act("WAIT_DMA_ACTIVATE",
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@ -81,7 +82,6 @@ class LiteSATACommandTX(Module):
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transport.sink.sop.eq(dwords_counter.value == 0),
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transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | sink.eop),
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transport.sink.type.eq(fis_types["DATA"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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If(sink.eop,
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@ -91,22 +91,19 @@ class LiteSATACommandTX(Module):
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)
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)
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)
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fsm.act("SEND_READ_DMA_OR_IDENTIFY_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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If(identify,
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transport.sink.command.eq(regs["IDENTIFY_DEVICE"]),
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self.comb += \
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If(fsm.ongoing("SEND_DATA"),
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transport.sink.type.eq(fis_types["DATA"]),
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).Else(
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transport.sink.command.eq(regs["READ_DMA_EXT"])
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),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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transport.sink.type.eq(fis_types["REG_H2D"]),
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If(is_write,
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transport.sink.command.eq(regs["WRITE_DMA_EXT"])
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).Elif(is_read,
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transport.sink.command.eq(regs["READ_DMA_EXT"]),
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).Else(
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transport.sink.command.eq(regs["IDENTIFY_DEVICE"]),
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)
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)
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)
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self.comb += [
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If(sink.stb,
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to_rx.write.eq(sink.write),
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@ -132,8 +129,8 @@ class LiteSATACommandRX(Module):
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def test_type(name):
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return transport.source.type == fis_types[name]
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identify = Signal()
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dma_activate = Signal()
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is_identify = Signal()
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is_dma_activate = Signal()
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read_ndwords = Signal(max=sectors2dwords(2**16))
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self.dwords_counter = dwords_counter = Counter(max=sectors2dwords(2**16))
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read_done = Signal()
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@ -169,13 +166,13 @@ class LiteSATACommandRX(Module):
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)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(from_tx.identify)
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is_identify.eq(from_tx.identify)
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)
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fsm.act("WAIT_WRITE_ACTIVATE_OR_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("DMA_ACTIVATE_D2H"),
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dma_activate.eq(1),
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is_dma_activate.eq(1),
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).Elif(test_type("REG_D2H"),
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set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
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NextState("PRESENT_WRITE_RESPONSE")
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@ -231,7 +228,7 @@ class LiteSATACommandRX(Module):
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If(data_buffer.sink.stb & data_buffer.sink.ack,
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self.dwords_counter.ce.eq(~read_done),
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If(data_buffer.sink.eop,
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If(read_done & ~identify,
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If(read_done & ~is_identify,
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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).Else(
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NextState("PRESENT_READ_RESPONSE")
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@ -248,16 +245,16 @@ class LiteSATACommandRX(Module):
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.read.eq(~identify),
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cmd_buffer.sink.identify.eq(identify),
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cmd_buffer.sink.last.eq(read_done | identify),
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cmd_buffer.sink.read.eq(~is_identify),
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cmd_buffer.sink.identify.eq(is_identify),
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cmd_buffer.sink.last.eq(read_done | is_identify),
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cmd_buffer.sink.success.eq(~read_error & ~d2h_error),
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cmd_buffer.sink.failed.eq(read_error | d2h_error),
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If(cmd_buffer.sink.stb & cmd_buffer.sink.ack,
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If(cmd_buffer.sink.failed,
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data_buffer.reset.eq(1)
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),
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If(read_done | identify,
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If(read_done | is_identify,
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NextState("IDLE")
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).Else(
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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@ -309,7 +306,7 @@ class LiteSATACommandRX(Module):
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)
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self.comb += [
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to_tx.dma_activate.eq(dma_activate),
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to_tx.dma_activate.eq(is_dma_activate),
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to_tx.d2h_error.eq(d2h_error)
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]
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