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build/xilinx/vivado: Allow passing str to add_false_path_constraint to allow mising Signals and str and simplify design constraints.

This commit is contained in:
Florent Kermarrec 2024-12-02 17:28:38 +01:00
parent 4e775a7bd6
commit ec06bf5955
1 changed files with 22 additions and 9 deletions
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31
litex/build/xilinx/vivado.py
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@ -199,31 +199,44 @@ class XilinxVivadoToolchain(GenericToolchain):
self.platform.add_platform_command( self.platform.add_platform_command(
"set_false_path -quiet " "set_false_path -quiet "
"-to [get_pins -filter {{REF_PIN_NAME == PRE}} " "-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
) )
# Set a maximum delay for metastability resolution in AsyncResetSynchronizer. # Set a maximum delay for metastability resolution in AsyncResetSynchronizer.
self.platform.add_platform_command( self.platform.add_platform_command(
"set_max_delay 2 -quiet " "set_max_delay 2 -quiet "
"-from [get_pins -filter {{REF_PIN_NAME == C}} " "-from [get_pins -filter {{REF_PIN_NAME == C}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] " "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} " "-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]" "-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]"
) )
# Add false paths between asynchronous clock domains. # Add false paths between asynchronous clock domains.
def get_clk_type(clk): def get_clk_type(clk):
return { return {
False : "nets", False: "nets",
True : "ports", True: "ports",
}[hasattr(clk, "port")] }[hasattr(clk, "port")]
for _from, _to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):
for _from, _to in sorted(self.false_paths, key=lambda x: (str(x[0]), str(x[1]))):
if isinstance(_from, str):
_from_cmd = f"[get_clocks {_from}]"
else:
_from_cmd = f"[get_clocks -include_generated_clocks -of [get_{get_clk_type(_from)} {{_from}}]]"
if isinstance(_to, str):
_to_cmd = f"[get_clocks {_to}]"
else:
_to_cmd = f"[get_clocks -include_generated_clocks -of [get_{get_clk_type(_to)} {{_to}}]]"
self.platform.add_platform_command( self.platform.add_platform_command(
"set_clock_groups " "set_clock_groups "
"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_from) + " {_from}]] " f"-group {_from_cmd} "
"-group [get_clocks -include_generated_clocks -of [get_" + get_clk_type(_to) + " {_to}]] " f"-group {_to_cmd} "
"-asynchronous", "-asynchronous",
_from=_from, _to=_to) _from = _from if not isinstance(_from, str) else None,
_to = _to if not isinstance(_to, str) else None,
)
# Clear false path constraints after generation. # Clear false path constraints after generation.
self.false_paths.clear() self.false_paths.clear()