bus/wishbone: target model
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@ -9,22 +9,18 @@ from migen.bus import wishbone
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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class MyPeripheral:
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class MyModel:
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def __init__(self):
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self.bus = wishbone.Interface()
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self.ack_en = Signal()
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self.prng = Random(763627)
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def do_simulation(self, s):
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# Only authorize acks on certain cycles to simulate variable latency.
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s.wr(self.ack_en, self.prng.randrange(0, 2))
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def read(self, address):
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return address + 4
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def get_fragment(self):
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comb = [
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self.bus.ack.eq(self.bus.cyc & self.bus.stb & self.ack_en),
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self.bus.dat_r.eq(self.bus.adr + 4)
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]
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return Fragment(comb, sim=[self.do_simulation])
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def write(self, address, data, sel):
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pass
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def can_ack(self, bus):
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return self.prng.randrange(0, 2)
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def adrgen_gen():
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for i in range(10):
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@ -47,7 +43,7 @@ def test_reader():
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g.add_connection(reader, dumper)
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comp = CompositeActor(g)
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peripheral = MyPeripheral()
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peripheral = wishbone.Target(MyModel())
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interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
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def end_simulation(s):
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@ -76,7 +72,7 @@ def test_writer():
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g.add_connection(trgen, writer)
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comp = CompositeActor(g)
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peripheral = MyPeripheral()
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peripheral = wishbone.Target(MyModel())
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tap = wishbone.Tap(peripheral.bus)
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interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
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@ -33,31 +33,26 @@ def my_generator():
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yield None
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# Our bus slave.
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# All transactions complete with a random delay.
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# Reads return address + 4. Writes are simply acknowledged.
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class MyPeripheral:
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class MyModel:
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def __init__(self):
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self.bus = wishbone.Interface()
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self.ack_en = Signal()
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self.prng = Random(763627)
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def do_simulation(self, s):
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# Only authorize acks on certain cycles to simulate variable latency.
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s.wr(self.ack_en, self.prng.randrange(0, 2))
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def read(self, address):
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return address + 4
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def get_fragment(self):
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comb = [
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self.bus.ack.eq(self.bus.cyc & self.bus.stb & self.ack_en),
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self.bus.dat_r.eq(self.bus.adr + 4)
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]
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return Fragment(comb, sim=[self.do_simulation])
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def write(self, address, data, sel):
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pass
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def can_ack(self, bus):
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return self.prng.randrange(0, 2)
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def main():
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# The "wishbone.Initiator" library component runs our generator
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# and manipulates the bus signals accordingly.
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master = wishbone.Initiator(my_generator())
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# Our slave.
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slave = MyPeripheral()
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# The "wishbone.Target" library component examines the bus signals
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# and calls into our model object.
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slave = wishbone.Target(MyModel())
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# The "wishbone.Tap" library component examines the bus at the slave port
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# and displays the transactions on the console (<TRead...>/<TWrite...>).
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tap = wishbone.Tap(slave.bus)
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@ -3,6 +3,7 @@ from migen.corelogic import roundrobin
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from migen.corelogic.misc import multimux, optree
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from migen.bus.simple import *
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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_desc = Description(
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(M_TO_S, "adr", 30),
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@ -186,3 +187,27 @@ class Initiator:
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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class Target:
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def __init__(self, model):
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self.bus = Interface()
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self.model = model
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def do_simulation(self, s):
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bus = Proxy(s, self.bus)
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if not bus.ack:
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if hasattr(self.model, "can_ack"):
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can_ack = self.model.can_ack(bus)
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else:
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can_ack = True
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if can_ack and bus.cyc and bus.stb:
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if bus.we:
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self.model.write(bus.adr, bus.dat_w, bus.sel)
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else:
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bus.dat_r = self.model.read(bus.adr)
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bus.ack = 1
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else:
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bus.ack = 0
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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