build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it)
This commit is contained in:
Florent Kermarrec
parent
1b963bb2d5
commit
ec7dc2d8f4
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@ -8,7 +8,6 @@
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# License: BSD
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import os
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import subprocess
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import sys
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@ -19,6 +18,7 @@ from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.xilinx import common
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# Constraints (.ucf) -------------------------------------------------------------------------------
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def _format_constraint(c):
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if isinstance(c, Pins):
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@ -30,7 +30,6 @@ def _format_constraint(c):
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elif isinstance(c, Misc):
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return c.misc
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def _format_ucf(signame, pin, others, resname):
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fmt_c = []
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for c in [Pins(pin)] + others:
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@ -42,7 +41,6 @@ def _format_ucf(signame, pin, others, resname):
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fmt_r += "." + resname[2]
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return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n"
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def _build_ucf(named_sc, named_pc):
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r = ""
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for sig, pins, others, resname in named_sc:
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@ -55,8 +53,9 @@ def _build_ucf(named_sc, named_pc):
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r += "\n" + "\n\n".join(named_pc)
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return r
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# Project (.xst) -----------------------------------------------------------------------------------
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def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):
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def _build_xst(device, sources, vincpaths, build_name, xst_opt):
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prj_contents = ""
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for filename, language, library in sources:
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prj_contents += language + " " + library + " " + tools.cygpath(filename) + "\n"
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@ -76,6 +75,7 @@ def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):
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xst_contents += "}"
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tools.write_to_file(build_name + ".xst", xst_contents)
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# Yosys Run ----------------------------------------------------------------------------------------
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def _run_yosys(device, sources, vincpaths, build_name):
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ys_contents = ""
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@ -103,6 +103,7 @@ write_edif -pvector bra {build_name}.edif""".format(build_name=build_name, famil
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if r != 0:
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raise OSError("Subprocess failed")
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# ISE Run ------------------------------------------------------------------------------------------
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def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
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toolchain, platform, ver=None):
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@ -164,33 +165,37 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit{fail_stmt}
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if r != 0:
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raise OSError("Subprocess failed")
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# XilinxISEToolchain --------------------------------------------------------------------------------
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class XilinxISEToolchain:
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attr_translate = {
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"keep": ("keep", "true"),
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"no_retiming": ("register_balancing", "no"),
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"async_reg": None,
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"mr_ff": None,
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"ars_ff1": None,
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"ars_ff2": None,
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"keep": ("keep", "true"),
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"no_retiming": ("register_balancing", "no"),
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"async_reg": None,
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"mr_ff": None,
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"ars_ff1": None,
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"ars_ff2": None,
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"no_shreg_extract": ("shreg_extract", "no")
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}
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def __init__(self):
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self.xst_opt = """-ifmt MIXED
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-use_new_parser yes
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-opt_mode SPEED
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-register_balancing yes"""
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self.xst_opt = "-ifmt MIXED\n-use_new_parser yes\n-opt_mode SPEED\n-register_balancing yes"
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self.map_opt = "-ol high -w"
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self.par_opt = "-ol high -w"
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self.ngdbuild_opt = ""
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self.bitgen_opt = "-g Binary:Yes -w"
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self.bitgen_opt = "-g Binary:Yes -w"
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self.ise_commands = ""
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def build(self, platform, fragment, build_dir="build", build_name="top",
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toolchain_path=None, source=True, run=True, mode="xst", **kwargs):
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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toolchain_path = None,
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source = True,
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run = True,
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mode = "xst",
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**kwargs):
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# Get default toolchain path (if not specified)
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if toolchain_path is None:
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if sys.platform == "win32":
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toolchain_path = "C:\\Xilinx"
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@ -199,35 +204,40 @@ class XilinxISEToolchain:
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else:
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toolchain_path = "/opt/Xilinx"
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platform.finalize(fragment)
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ngdbuild_opt = self.ngdbuild_opt
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vns = None
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# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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vns = None
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try:
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if mode in ("xst", "yosys", "cpld"):
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if mode in ["xst", "yosys", "cpld"]:
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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vns = v_output.ns
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named_sc, named_pc = platform.resolve_signals(vns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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if mode in ("xst", "cpld"):
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_build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
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# Generate design project (.xst)
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if mode in ["xst", "cpld"]:
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_build_xst(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
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isemode = mode
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else:
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# Run Yosys
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if run:
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_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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isemode = "edif"
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ngdbuild_opt += "-p " + platform.device
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self.ngdbuild_opt += "-p " + platform.device
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if mode == "mist":
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from mist import synthesize
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synthesize(fragment, platform.constraint_manager.get_io_signals())
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if mode == "edif" or mode == "mist":
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if mode in ["edif"]:
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# Generate edif
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e_output = platform.get_edif(fragment)
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vns = e_output.ns
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named_sc, named_pc = platform.resolve_signals(vns)
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@ -235,10 +245,12 @@ class XilinxISEToolchain:
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e_output.write(e_file)
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isemode = "edif"
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# Generate design constraints (.ucf)
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tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
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# Run ISE
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if run:
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_run_ise(build_name, toolchain_path, source, isemode,
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ngdbuild_opt, self, platform)
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_run_ise(build_name, toolchain_path, source, isemode, self.ngdbuild_opt, self, platform)
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finally:
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os.chdir(cwd)
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