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platforms/kcu105: set internal vref on ddr4 banks
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@ -483,3 +483,9 @@ class Platform(XilinxPlatform):
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_platform_command("set_property INTERNAL_VREF {{0.60}} [get_iobanks 44]")
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self.add_platform_command("set_property INTERNAL_VREF {{0.60}} [get_iobanks 45]")
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self.add_platform_command("set_property INTERNAL_VREF {{0.60}} [get_iobanks 46]")
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