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Merge pull request #2056 from trabucayre/altera_agilex5_asyncresetsynchronizer 

build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
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enjoy-digital 2024-09-03 17:54:27 +02:00 committed by GitHub
parent dc29b6f4e5 d0215001f4
commit eda553aeaa
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1 changed files with 19 additions and 1 deletions
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litex/build/altera/common.py
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@ -147,6 +147,24 @@ altera_special_overrides = {
SDRInput: AlteraSDRInput, SDRInput: AlteraSDRInput,
} }
# Agilex5 AsyncResetSynchronizer -------------------------------------------------------------------
class Agilex5AsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
self.specials += Instance("altera_std_synchronizer_nocut", name=f"ars_cd_{cd.name}_ff0",
p_depth = 3,
p_rst_value = 0,
i_clk = cd.clk,
i_reset_n = Constant(1, 1),
i_din = async_reset,
o_dout = cd.rst,
)
class Agilex5AsyncResetSynchronizer:
@staticmethod
def lower(dr):
return Agilex5AsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
# Agilex5 DDROutput -------------------------------------------------------------------------------- # Agilex5 DDROutput --------------------------------------------------------------------------------
class Agilex5DDROutputImpl(Module): class Agilex5DDROutputImpl(Module):
@ -237,7 +255,7 @@ class Agilex5SDRTristate(Module):
# Agilex5 Special Overrides ------------------------------------------------------------------------ # Agilex5 Special Overrides ------------------------------------------------------------------------
agilex5_special_overrides = { agilex5_special_overrides = {
AsyncResetSynchronizer: AlteraAsyncResetSynchronizer, AsyncResetSynchronizer: Agilex5AsyncResetSynchronizer,
DifferentialInput: AlteraDifferentialInput, DifferentialInput: AlteraDifferentialInput,
DifferentialOutput: AlteraDifferentialOutput, DifferentialOutput: AlteraDifferentialOutput,
DDROutput: Agilex5DDROutput, DDROutput: Agilex5DDROutput,