boards: add Lambdaconcept's PCIe Screamer (R02)
This commit is contained in:
Florent Kermarrec
parent
a8635c48a4
commit
edaa66bbed
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# This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019 Pierre-Olivier Vauboin <po@lambdaconcept>
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# License: BSD
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("T1")),
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Subsignal("rx", Pins("U1")),
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IOStandard("LVCMOS33"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M2 M5 M3 M1 L6 P1 N3 N2",
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"M6 R1 L5 N5 N4 P2 P6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"G2 H4 H5 J1 K1 H3 H2 J5",
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"E3 B2 F3 D2 C2 A1 E2 B1"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("AB7"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B10")),
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Subsignal("rx_n", Pins("A10")),
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Subsignal("tx_p", Pins("B6")),
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Subsignal("tx_n", Pins("A6"))
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),
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("usb_fifo_clock", 0, Pins("D17"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst", Pins("K22")),
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Subsignal("data", Pins(
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"A16 F14 A15 F13 A14 E14 A13 E13",
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"B13 C15 C13 C14 B16 E17 B15 F16",
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"A20 E18 B20 F18 D19 D21 E19 E21",
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"A21 B21 A19 A18 F20 F19 B18 B17")),
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Subsignal("be", Pins("K16 L16 G20 H20")),
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Subsignal("rxf_n", Pins("M13")),
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Subsignal("txe_n", Pins("L13")),
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Subsignal("rd_n", Pins("K19")),
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Subsignal("wr_n", Pins("M15")),
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Subsignal("oe_n", Pins("K18")),
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Subsignal("siwua", Pins("M16")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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@ -0,0 +1,81 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex.boards.platforms import pcie_screamer
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
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platform = pcie_screamer.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41K128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on PCIe Screamer")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args))
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if __name__ == "__main__":
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main()
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