Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc_core/soc_core_args: specify default cpu (vexriscv)

Browse source
This commit is contained in:
Florent Kermarrec 2019-11-01 11:30:50 +01:00
parent cc607f022a
commit edb1731ef9
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/integration/soc_core.py
View file

@ -540,7 +540,7 @@ class SoCCore(Module):
def soc_core_args(parser):
# CPU parameters
parser.add_argument("--cpu-type", default=None,
help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys()))))
help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
parser.add_argument("--cpu-variant", default=None,
help="select CPU variant, (default=standard)")
parser.add_argument("--cpu-reset-address", default=None, type=int,