soc/cores/cpu: Add initial uRV CPU support (not yet working).
This commit is contained in:
Florent Kermarrec
parent
c82fddf635
commit
edb56e73aa
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from litex.soc.cores.cpu.urv.core import uRV
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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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jr x13
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = {
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"standard": "urv",
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}
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# GCC Flags ----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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# /------------ Base ISA
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# | /------- Hardware Multiply + Divide
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# | |/----- Atomics
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# | ||/---- Compressed ISA
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# | |||/--- Single-Precision Floating-Point
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# | ||||/-- Double-Precision Floating-Point
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# i macfd
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"standard": "-march=rv32i2p0_m -mabi=ilp32",
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}
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# uRV ------------------------------------------------------------------------------------------
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class uRV(CPU):
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category = "softcore"
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family = "riscv"
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name = "urv"
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human_name = "urv"
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variants = CPU_VARIANTS
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x8000_0000: 0x8000_0000} # Origin, Length.
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# GCC Flags.
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += " -D__urv__ "
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.human_name = f"uRV-{variant.upper()}"
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self.reset = Signal()
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self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# uRV Signals.
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# ------------
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im_addr = Signal(32)
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im_rd = Signal(1)
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im_data = Signal(32)
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im_valid = Signal(1)
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dm_addr = Signal(32)
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dm_data_s = Signal(32)
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dm_data_l = Signal(32)
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dm_data_select = Signal(4)
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dm_store = Signal()
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dm_load = Signal()
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dm_load_done = Signal()
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dm_store_done = Signal()
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rst_count = Signal(8, reset=16)
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self.sync += If(rst_count != 0, rst_count.eq(rst_count - 1))
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# uRV Instance.
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# -------------
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self.cpu_params = dict(
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# Parameters.
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p_g_timer_frequency = 1000,
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p_g_clock_frequency = 100000000,
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p_g_with_hw_div = 1,
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p_g_with_hw_mulh = 1,
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p_g_with_hw_mul = 1,
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p_g_with_hw_debug = 0,
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p_g_with_ecc = 0,
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p_g_with_compressed_insns = 0,
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# Clk / Rst.
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i_clk_i = ClockSignal("sys"),
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i_rst_i = ~(ResetSignal("sys") | self.reset | (rst_count != 0)),
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# Instruction Mem Bus.
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o_im_addr_o = im_addr,
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o_im_rd_o = im_rd,
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i_im_data_i = im_data,
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i_im_valid_i = im_valid,
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# Data Mem Bus.
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o_dm_addr_o = dm_addr,
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o_dm_data_s_o = dm_data_s,
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i_dm_data_l_i = dm_data_l,
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o_dm_data_select_o = dm_data_select,
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o_dm_store_o = dm_store,
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o_dm_load_o = dm_load,
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i_dm_load_done_i = dm_load_done,
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i_dm_store_done_i = dm_store_done,
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)
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# uRV Instruction Bus.
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# --------------------
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self.i_fsm = i_fsm = FSM(reset_state="IDLE")
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i_fsm.act("IDLE",
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If(im_rd,
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NextValue(im_valid, 0),
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NextState("READ")
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)
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)
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i_fsm.act("READ",
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ibus.stb.eq(1),
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ibus.cyc.eq(1),
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ibus.we.eq(0),
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ibus.adr.eq(im_addr),
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ibus.sel.eq(0b1111),
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If(ibus.ack,
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NextValue(im_valid, 1),
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NextValue(im_data, ibus.dat_r),
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NextState("IDLE")
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)
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)
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# uRV Data Bus.
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# -------------
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self.d_fsm = d_fsm = FSM(reset_state="IDLE")
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d_fsm.act("IDLE",
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If(dm_store,
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NextState("WRITE")
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),
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If(dm_load,
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NextState("READ")
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)
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)
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d_fsm.act("WRITE",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(1),
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dbus.adr.eq(dm_addr),
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dbus.sel.eq(dm_data_select),
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dbus.dat_w.eq(dm_data_s),
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If(dbus.ack,
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NextState("IDLE")
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)
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)
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d_fsm.act("READ",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(0),
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dbus.adr.eq(dm_addr),
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dbus.sel.eq(dm_data_select),
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If(dbus.ack,
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dm_load_done.eq(1),
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dm_data_l.eq(dbus.dat_r),
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NextState("IDLE")
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)
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)
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# Add Verilog sources.
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# --------------------
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self.add_sources(platform, variant)
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def set_reset_address(self, reset_address):
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assert reset_address == 0
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self.reset_address = reset_address
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@staticmethod
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def add_sources(platform, variant):
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if not os.path.exists("urv-core"):
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os.system(f"git clone https://ohwr.org/project/urv-core/")
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vdir = "urv-core/rtl"
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platform.add_verilog_include_path("urv-core/rtl")
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platform.add_sources([
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"urv-core/rtl/urv_cpu.v",
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"urv-core/rtl/urv_exec.v",
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"urv-core/rtl/urv_fetch.v",
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"urv-core/rtl/urv_decode.v",
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"urv-core/rtl/urv_regfile.v",
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"urv-core/rtl/urv_writeback.v",
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"urv-core/rtl/urv_shifter.v",
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"urv-core/rtl/urv_multiply.v",
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"urv-core/rtl/urv_divide.v",
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"urv-core/rtl/urv_csr.v",
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"urv-core/rtl/urv_timer.v",
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"urv-core/rtl/urv_exceptions.v",
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"urv-core/rtl/urv_iram.v",
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"urv-core/rtl/urv_ecc.v",
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])
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def do_finalize(self):
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self.specials += Instance("urv_cpu", **self.cpu_params)
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@ -0,0 +1,75 @@
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#define MIE_MEIE 0x800
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.global _start
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_start:
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j reset_vector
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reset_vector:
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la sp, _fstack
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la t0, trap_vector
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csrw mtvec, t0
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// initialize .data
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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1: beq t0, t1, 2f
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lw t3, 0(t2)
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sw t3, 0(t0)
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addi t0, t0, 4
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addi t2, t2, 4
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j 1b
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2:
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// initialize .bss
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la t0, _fbss
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la t1, _ebss
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1: beq t0, t1, 3f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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3:
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// enable external interrupts
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li t0, MIE_MEIE
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csrs mie, t0
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call main
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1: j 1b
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trap_vector:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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sw t1, 2*4(sp)
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sw t2, 3*4(sp)
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sw a0, 4*4(sp)
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sw a1, 5*4(sp)
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sw a2, 6*4(sp)
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sw a3, 7*4(sp)
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sw a4, 8*4(sp)
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sw a5, 9*4(sp)
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sw a6, 10*4(sp)
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sw a7, 11*4(sp)
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sw t3, 12*4(sp)
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sw t4, 13*4(sp)
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sw t5, 14*4(sp)
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sw t6, 15*4(sp)
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call isr
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lw ra, 0*4(sp)
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lw t0, 1*4(sp)
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lw t1, 2*4(sp)
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lw t2, 3*4(sp)
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lw a0, 4*4(sp)
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lw a1, 5*4(sp)
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lw a2, 6*4(sp)
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lw a3, 7*4(sp)
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lw a4, 8*4(sp)
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lw a5, 9*4(sp)
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lw a6, 10*4(sp)
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lw a7, 11*4(sp)
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lw t3, 12*4(sp)
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lw t4, 13*4(sp)
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lw t5, 14*4(sp)
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lw t6, 15*4(sp)
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addi sp, sp, 16*4
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mret
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@ -0,0 +1,4 @@
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#ifndef __IRQ_H
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#define __IRQ_H
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#endif /* __IRQ_H */
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@ -0,0 +1,19 @@
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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_H */
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