cores/clock: add initial iCE40 support
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@ -382,6 +382,101 @@ class USIDELAYCTRL(Module):
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i_REFCLK=cd.clk,
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i_RST=ic_reset)
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# Lattice / iCE40 ----------------------------------------------------------------------------------
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# TODO:
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# - add phase support.
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# - add support for GENCLK_HALF to be able to generate clock down to 8MHz.
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class iCE40PLL(Module):
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nclkouts_max = 1
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divr_range = (0, 16)
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divf_range = (0, 128)
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divq_range = (0, 7)
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clki_freq_range = ( 10e6, 133e9)
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clko_freq_range = ( 16e6, 275e9)
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vco_freq_range = (533e6, 1066e6)
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def __init__(self):
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.clkouts = {}
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self.config = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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assert freq >= clki_freq_min
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assert freq <= clki_freq_max
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self.clkin = Signal()
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if isinstance(clkin, (Signal, ClockSignal)):
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self.comb += self.clkin.eq(clkin)
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else:
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raise ValueError
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self.clkin_freq = freq
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def create_clkout(self, cd, freq, margin=1e-2):
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(clko_freq_min, clko_freq_max) = self.clko_freq_range
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assert freq >= clko_freq_min
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assert freq <= clko_freq_max
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assert self.nclkouts < self.nclkouts_max
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clkout = Signal()
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self.clkouts[self.nclkouts] = (clkout, freq, 0, margin)
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self.nclkouts += 1
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self.comb += cd.clk.eq(clkout)
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def compute_config(self):
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config = {}
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for divr in range(*self.divr_range):
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for divf in range(*self.divf_range):
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all_valid = True
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vco_freq = self.clkin_freq/(divr + 1)*(divf + 1)
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for divq in range(*self.divq_range):
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clk_freq = vco_freq/(2**divq)
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if abs(clk_freq - f) < f*m:
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config["divq"] = divq
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valid = True
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["divr"] = divr
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config["divf"] = divf
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return config
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raise ValueError("No PLL config found")
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def do_finalize(self):
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config = self.compute_config()
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clkfb = Signal()
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for f, v in [(17e6, 1), (26e6, 2), (44e6, 3), (66e6, 4), (101e6, 5), (133e6, 6)]:
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pfd_freq = self.clkin_freq/(config["divr"] + 1)
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if pfd_freq < f:
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filter_range = v
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break
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self.params.update(
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p_FEEDBACK_PATH="SIMPLE",
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p_FILTER_RANGE=filter_range,
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i_RESETB=~self.reset,
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i_REFERENCECLK=self.clkin,
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o_LOCK=self.locked,
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_DIVR"] = config["divr"]
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self.params["p_DIVF"] = config["divf"]
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self.params["p_DIVQ"] = config["divq"]
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self.params["o_PLLOUTGLOBAL"] = clk
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self.specials += Instance("SB_PLL40_CORE", **self.params)
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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# TODO:
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