boards: add nexys4ddr
This commit is contained in:
Florent Kermarrec
parent
2ecd1b0666
commit
ee4fa597b4
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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
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_io = [
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("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("N14"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("R18"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("V17"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("U17"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("U16"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("V16"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("T15"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("U14"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("T16"), IOStandard("LVCMOS33")),
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("user_led", 12, Pins("V15"), IOStandard("LVCMOS33")),
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("user_led", 13, Pins("V14"), IOStandard("LVCMOS33")),
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("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")),
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("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("D4")),
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Subsignal("rx", Pins("C4")),
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IOStandard("LVCMOS33"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"M4 P4 M6 T1 L3 P5 M2 N1",
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"L4 N5 R2 K5 N6"),
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IOStandard("SSTL18_II")),
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Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")),
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Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")),
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Subsignal("cas_n", Pins("L3"), IOStandard("SSTL18_II")),
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Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")),
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Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")),
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Subsignal("dq", Pins(
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"R7 V6 R8 U7 V7 R6 U6 R5",
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"T5 U3 V5 U4 V4 T4 V1 T3"),
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IOStandard("SSTL18_II"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("U9 U2"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")),
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Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")),
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Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
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Misc("SLEW=FAST"),
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),
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self, programmer="vivado"):
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XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
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self.programmer = programmer
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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def create_programmer(self):
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if self.programmer == "xc3sprog":
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return XC3SProg("nexys4")
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elif self.programmer == "vivado":
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return VivadoProgrammer()
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else:
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raise ValueError("{} programmer is not supported"
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.format(self.programmer))
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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@ -0,0 +1,117 @@
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#!/usr/bin/env python3
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import argparse
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from litex.gen import *
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from litex.gen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import nexys4ddr
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K256M16
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from litedram.phy import a7ddrphy
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk100 = ClockDomain()
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset")
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pll_locked = Signal()
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pll_fb = Signal()
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self.pll_sys = Signal()
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pll_sys4x = Signal()
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pll_sys4x_dqs = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1600 MHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 100 MHz
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p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=self.pll_sys,
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# 400 MHz
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p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys4x,
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# 400 MHz dqs
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p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
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o_CLKOUT2=pll_sys4x_dqs,
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# 200 MHz
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p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
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o_CLKOUT3=pll_clk200
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),
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Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"ddrphy": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, **kwargs):
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platform = nexys4ddr.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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# sdram
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self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
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self.add_constant("READ_LEVELING_BITSLIP", 3)
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self.add_constant("READ_LEVELING_DELAY", 14)
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sdram_module = MT41K256M16(self.clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC port to Nexys4DDR")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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