Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

Wishbone DownConverter: Fix sel signal

Browse source
This commit is contained in:
Yann Sionneau 2014-11-26 12:10:20 +01:00 committed by Sebastien Bourdeauducq
parent 4542de2c11
commit ee928a8973
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
migen/bus/wishbone.py
View file

@ -154,7 +154,7 @@ class DownConverter(Module):
# direct connection of wishbone_i --> wishbone_o signals
for name, size, direction in self.wishbone_i.layout:
if direction == DIR_M_TO_S and name not in ["adr", "dat_w"]:
if direction == DIR_M_TO_S and name not in ["adr", "dat_w", "sel"]:
self.comb += getattr(self.wishbone_o, name).eq(getattr(self.wishbone_i, name))
# adaptation of adr & dat signals
@ -164,6 +164,7 @@ class DownConverter(Module):
]
self.comb += chooser(dat_w, cnt, self.wishbone_o.dat_w, reverse=True)
self.comb += chooser(self.wishbone_i.sel, cnt, self.wishbone_o.sel, reverse=True)
# fsm
fsm = FSM(reset_state="IDLE")