add mode generic CommandGenerator for debug
This commit is contained in:
Florent Kermarrec
parent
9dc6903c55
commit
eebc2abcda
123
targets/test.py
123
targets/test.py
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@ -152,38 +152,116 @@ class ClockLeds(Module):
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sata_tx_cnt.eq(sata_tx_cnt-1)
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)
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class IdentifyRequester(Module, AutoCSR):
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def __init__(self, sata_con):
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self._req = CSRStorage()
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req = self._req.storage
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class CommandGenerator(Module, AutoCSR):
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def __init__(self, sata_con, sector_size):
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self._write = CSR()
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self._read = CSR()
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self._identify = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._data = CSRStorage(32) # Note: fixed data, add a fifo later
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req_d = Signal()
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self._sucess = CSRStatus()
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self._failed = CSRStatus()
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self.fsm = fsm = FSM(reset_state="IDLE")
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def new_command(csr):
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return csr.r & csr.re
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cnt = Signal(16)
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sector = self._sector.storage
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count = self._count.storage
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data = self._data.storage
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success = self._sucess.status
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failed = self._failed.status
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clr_status = Signal()
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set_success = Signal()
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set_failed = Signal()
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self.sync += [
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req_d.eq(req),
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If(req & ~req_d,
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sata_con.sink.stb.eq(1)
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).Elif(sata_con.sink.ack,
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sata_con.sink.stb.eq(0)
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If(clr_status,
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success.eq(0),
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failed.eq(0),
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).Elif(set_success,
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success.eq(1)
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).Elif(set_failed,
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failed.eq(1)
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)
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]
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self.comb += [
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self.comb += sata_con.source.ack.eq(1)
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# FSM
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fsm.act("IDLE",
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clr_status.eq(1),
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If(new_command(self._write),
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NextState("SEND_WRITE_CMD")
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).Elif(new_command(self._read),
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NextState("SEND_READ_CMD")
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).Elif(new_command(self._identify),
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NextState("SEND_IDENTIFY_CMD")
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)
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)
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fsm.act("SEND_WRITE_CMD",
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sata_con.sink.stb.eq(1),
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sata_con.sink.sop.eq(cnt == 0),
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sata_con.sink.eop.eq(cnt == (count*sector_size-1)),
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sata_con.sink.write.eq(1),
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sata_con.sink.sector.eq(sector),
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sata_con.sink.count.eq(count),
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sata_con.sink.data.eq(data),
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If(sata_con.sink.eop & sata_con.sink.ack,
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NextState("WAIT_WRITE_ACK")
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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# XXX: add check of success / failed
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If(sata_con.source.stb & sata_con.source.eop,
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set_success.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("SEND_READ_CMD",
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sata_con.sink.stb.eq(1),
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sata_con.sink.sop.eq(1),
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sata_con.sink.eop.eq(1),
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sata_con.sink.read.eq(1),
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sata_con.sink.sector.eq(sector),
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sata_con.sink.count.eq(count),
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If(sata_con.sink.ack,
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NextState("WAIT_READ_ACK_AND_DATA")
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)
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)
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fsm.act("WAIT_READ_ACK_AND_DATA",
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# XXX: add check of success / failed and receive data
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If(sata_con.source.stb & sata_con.source.eop,
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set_success.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("SEND_IDENTIFY_CMD",
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sata_con.sink.stb.eq(1),
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sata_con.sink.sop.eq(1),
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sata_con.sink.eop.eq(1),
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sata_con.sink.identify.eq(1),
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sata_con.sink.sector.eq(0),
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sata_con.sink.count.eq(1),
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sata_con.sink.data.eq(0),
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sata_con.sink.ack.eq(1),
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]
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If(sata_con.sink.ack,
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NextState("WAIT_IDENTIFY_ACK_AND_DATA")
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)
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)
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fsm.act("WAIT_IDENTIFY_ACK_AND_DATA",
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# XXX: add check of success / failed and receive data
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If(sata_con.source.stb & sata_con.source.eop,
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set_success.eq(1),
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NextState("IDLE")
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)
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)
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class TestDesign(UART2WB, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"mila": 10,
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"identify_requester": 11
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"command_generator": 11
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}
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csr_map.update(UART2WB.csr_map)
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@ -195,7 +273,7 @@ class TestDesign(UART2WB, AutoCSR):
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self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2")
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self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
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self.identify_requester = IdentifyRequester(self.sata_con)
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self.command_generator = CommandGenerator(self.sata_con, sector_size=512)
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self.clock_leds = ClockLeds(platform)
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@ -226,15 +304,12 @@ class TestDesign(UART2WB, AutoCSR):
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self.sata_phy.sink.data,
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self.sata_phy.sink.charisk,
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self.sata_phy.datapath.tx.sink.stb,
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self.sata_phy.datapath.tx.sink.data,
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self.sata_phy.datapath.tx.sink.charisk,
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self.sata_phy.datapath.tx.sink.ack,
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self.sata_con.sink.stb,
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self.sata_con.sink.sop,
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self.sata_con.sink.eop,
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self.sata_con.sink.ack,
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self.sata_con.sink.write,
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self.sata_con.sink.read,
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self.sata_con.sink.identify,
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self.sata_con.source.stb,
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@ -1,71 +1,31 @@
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import time
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from config import *
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from miscope.host.dump import *
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from tools import *
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from miscope.host.drivers import MiLaDriver
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mila = MiLaDriver(wb.regs, "mila", use_rle=False)
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mila = MiLaDriver(wb.regs, "mila")
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wb.open()
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regs = wb.regs
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###
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trigger0 = mila.sata_con_sink_stb_o*1
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mask0 = mila.sata_con_sink_stb_m
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#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
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#mask0 = mila.sata_phy_source_source_payload_data_m
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trigger0 = mila.sata_con_sink_payload_identify_o*1
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mask0 = mila.sata_con_sink_payload_identify_m
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mila.prog_term(port=0, trigger=trigger0, mask=mask0)
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mila.prog_sum("term")
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# Trigger / wait / receive
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mila.trigger(offset=32, length=256)
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regs.identify_requester_req.write(1)
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regs.identify_requester_req.write(0)
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mila.trigger(offset=32, length=512)
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regs.command_generator_identify.write(1)
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mila.wait_done()
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mila.read()
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mila.export("dump.vcd")
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mila.export("dump.csv")
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mila.export("dump.py")
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###
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wb.close()
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###
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primitives = {
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"ALIGN" : 0x7B4A4ABC,
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"CONT" : 0X9999AA7C,
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"SYNC" : 0xB5B5957C,
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"R_RDY" : 0x4A4A957C,
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"R_OK" : 0x3535B57C,
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"R_ERR" : 0x5656B57C,
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"R_IP" : 0X5555B57C,
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"X_RDY" : 0x5757B57C,
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"CONT" : 0x9999AA7C,
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"WTRM" : 0x5858B57C,
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"SOF" : 0x3737B57C,
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"EOF" : 0xD5D5B57C,
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"HOLD" : 0xD5D5AA7C,
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"HOLDA" : 0X9595AA7C
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}
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def decode_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return k
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return ""
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dump = Dump()
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dump.add_from_layout(mila.layout, mila.dat)
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for var in dump.vars:
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if var.name == "sata_phy_sink_sink_payload_data":
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tx_data = var.values
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if var.name == "sata_phy_source_source_payload_data":
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rx_data = var.values
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for i in range(len(tx_data)):
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tx = "%08x " %tx_data[i]
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tx += decode_primitive(tx_data[i])
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tx += " "*(16-len(tx))
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rx = "%08x " %rx_data[i]
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rx += decode_primitive(rx_data[i])
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rx += " "*(16-len(rx))
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print(tx + rx)
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print_link_trace(mila,
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tx_data_name="sata_phy_sink_sink_payload_data",
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rx_data_name="sata_phy_source_source_payload_data"
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)
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@ -0,0 +1,45 @@
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from miscope.host.dump import *
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primitives = {
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"ALIGN" : 0x7B4A4ABC,
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"CONT" : 0X9999AA7C,
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"SYNC" : 0xB5B5957C,
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"R_RDY" : 0x4A4A957C,
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"R_OK" : 0x3535B57C,
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"R_ERR" : 0x5656B57C,
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"R_IP" : 0X5555B57C,
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"X_RDY" : 0x5757B57C,
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"CONT" : 0x9999AA7C,
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"WTRM" : 0x5858B57C,
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"SOF" : 0x3737B57C,
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"EOF" : 0xD5D5B57C,
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"HOLD" : 0xD5D5AA7C,
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"HOLDA" : 0X9595AA7C
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}
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def decode_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return k
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return ""
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def print_link_trace(mila, tx_data_name, rx_data_name):
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dump = Dump()
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dump.add_from_layout(mila.layout, mila.dat)
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for var in dump.vars:
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if var.name == tx_data_name:
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tx_data = var.values
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if var.name == rx_data_name:
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rx_data = var.values
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for i in range(len(tx_data)):
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tx = "%08x " %tx_data[i]
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tx += decode_primitive(tx_data[i])
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tx += " "*(16-len(tx))
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rx = "%08x " %rx_data[i]
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rx += decode_primitive(rx_data[i])
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rx += " "*(16-len(rx))
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print(tx + rx)
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