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fhdl: support Constant parameters for Verilog conversion

This commit is contained in:
Sebastien Bourdeauducq 2011-12-11 20:17:51 +01:00
parent dafef5d744
commit eee6980a36
1 changed files with 5 additions and 3 deletions
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8
migen/fhdl/verilog.py
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@ -88,15 +88,17 @@ def _printinstances(ns, i, clk, rst):
r += ",\n" r += ",\n"
firstp = False firstp = False
r += "\t." + p[0] + "(" r += "\t." + p[0] + "("
if isinstance(p[1], int): if isinstance(p[1], int) or isinstance(p[1], Constant):
r += str(p[1]) r += str(p[1])
elif isinstance(p[1], basestring): elif isinstance(p[1], str):
r += "\"" + p[1] + "\"" r += "\"" + p[1] + "\""
else: else:
raise TypeError raise TypeError
r += ")" r += ")"
r += "\n) " r += "\n) "
r += ns.GetName(x) + "(\n" r += ns.GetName(x)
if x.parameters: r += " "
r += "(\n"
ports = list(x.ins.items()) + list(x.outs.items()) ports = list(x.ins.items()) + list(x.outs.items())
if x.clkport: if x.clkport:
ports.append((x.clkport, clk)) ports.append((x.clkport, clk))