litex/gen: remove io that has been replaced with litex/build/io (and should have been removed).
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litex/gen/io.py
113
litex/gen/io.py
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.fhdl.specials import Special
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# Differential Input/Output ------------------------------------------------------------------------
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class DifferentialInput(Special):
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def __init__(self, i_p, i_n, o):
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Special.__init__(self)
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self.i_p = wrap(i_p)
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self.i_n = wrap(i_n)
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self.o = wrap(o)
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def iter_expressions(self):
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yield self, "i_p", SPECIAL_INPUT
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yield self, "i_n", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a differential input, but platform does not support them")
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class DifferentialOutput(Special):
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def __init__(self, i, o_p, o_n):
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Special.__init__(self)
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self.i = wrap(i)
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self.o_p = wrap(o_p)
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self.o_n = wrap(o_n)
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o_p", SPECIAL_OUTPUT
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yield self, "o_n", SPECIAL_OUTPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
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# SDR Input/Output ---------------------------------------------------------------------------------
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class InferedSDRIO(Module):
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def __init__(self, i, o, clk, clk_domain):
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if clk_domain is None:
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raise NotImplementedError("Attempted to use an InferedSDRIO but no clk_domain specified.")
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sync = getattr(self.sync, clk_domain)
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sync += o.eq(i)
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class SDRIO(Special):
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def __init__(self, i, o, clk=ClockSignal()):
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assert len(i) == len(o)
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Special.__init__(self)
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print(o)
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self.i = wrap(i)
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self.o = wrap(o)
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self.clk = wrap(clk)
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self.clk_domain = None if not hasattr(clk, "cd") else clk.cd
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain)
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class SDRInput(SDRIO): pass
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class SDROutput(SDRIO): pass
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# DDR Input/Output ---------------------------------------------------------------------------------
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class DDRInput(Special):
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def __init__(self, i, o1, o2, clk=ClockSignal()):
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Special.__init__(self)
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self.i = wrap(i)
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self.o1 = wrap(o1)
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self.o2 = wrap(o2)
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self.clk = wrap(clk)
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o1", SPECIAL_OUTPUT
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yield self, "o2", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a DDR input, but platform does not support them")
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class DDROutput(Special):
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def __init__(self, i1, i2, o, clk=ClockSignal()):
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Special.__init__(self)
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self.i1 = i1
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self.i2 = i2
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self.o = o
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self.clk = clk
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def iter_expressions(self):
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yield self, "i1", SPECIAL_INPUT
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yield self, "i2", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
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