bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY

examples/simple_gpio.py

@@ -1,17 +1,18 @@
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
 from migen.bank import description, csrgen
+from migen.bank.description import READ_ONLY, WRITE_ONLY
 
-ninputs = 4
+ninputs = 32
-noutputs = 31
+noutputs = 32
 
 oreg = description.RegisterField("o", noutputs)
-ireg = description.RegisterRaw("i", ninputs)
+ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY)
 
 # input path
 gpio_in = Signal(BV(ninputs))
 gpio_in_s = Signal(BV(ninputs)) # synchronizer
-insync = [gpio_in_s.eq(gpio_in), ireg.w.eq(gpio_in_s)]
+insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)]
 inf = Fragment(sync=insync)
 
 bank = csrgen.Bank([oreg, ireg])

migen/bank/csrgen.py

@@ -71,6 +71,9 @@ class Bank:
 		for reg in self.description:
 			if isinstance(reg, RegisterFields):
 				for field in reg.fields:
+					if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY:
+						comb.append(field.storage.eq(field.w))
+					else:
 						if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
 							comb.append(field.r.eq(field.storage))
 						if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:

migen/bank/description.py

@@ -17,6 +17,9 @@ class Field:
 		self.access_bus = access_bus
 		self.access_dev = access_dev
 		self.storage = Signal(BV(self.size), reset=reset)
+		if self.access_bus == READ_ONLY and self.access_dev == WRITE_ONLY:
+			self.w = Signal(BV(self.size))
+		else:
 			if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
 				self.r = Signal(BV(self.size))
 			if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE: