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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY

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This commit is contained in:
Sebastien Bourdeauducq 2012-02-15 18:23:31 +01:00
parent fa9cf3e466
commit ef7aea0f31
3 changed files with 19 additions and 12 deletions
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9
examples/simple_gpio.py
View file

@ -1,17 +1,18 @@
from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.bank import description, csrgen
from migen.bank.description import READ_ONLY, WRITE_ONLY
ninputs = 4
noutputs = 31
ninputs = 32
noutputs = 32
oreg = description.RegisterField("o", noutputs)
ireg = description.RegisterRaw("i", ninputs)
ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY)
# input path
gpio_in = Signal(BV(ninputs))
gpio_in_s = Signal(BV(ninputs)) # synchronizer
insync = [gpio_in_s.eq(gpio_in), ireg.w.eq(gpio_in_s)]
insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)]
inf = Fragment(sync=insync)
bank = csrgen.Bank([oreg, ireg])

11
migen/bank/csrgen.py
View file

@ -71,9 +71,12 @@ class Bank:
for reg in self.description:
if isinstance(reg, RegisterFields):
for field in reg.fields:
if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
comb.append(field.r.eq(field.storage))
if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
sync.append(If(field.we, field.storage.eq(field.w)))
if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY:
comb.append(field.storage.eq(field.w))
else:
if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
comb.append(field.r.eq(field.storage))
if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
sync.append(If(field.we, field.storage.eq(field.w)))
return Fragment(comb, sync)

11
migen/bank/description.py
View file

@ -17,11 +17,14 @@ class Field:
self.access_bus = access_bus
self.access_dev = access_dev
self.storage = Signal(BV(self.size), reset=reset)
if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
self.r = Signal(BV(self.size))
if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
if self.access_bus == READ_ONLY and self.access_dev == WRITE_ONLY:
self.w = Signal(BV(self.size))
self.we = Signal()
else:
if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
self.r = Signal(BV(self.size))
if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
self.w = Signal(BV(self.size))
self.we = Signal()
class RegisterFields:
def __init__(self, name, fields):