Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

generic_platform/get_verilog: pass additional args to verilog.convert

This commit is contained in:
Sebastien Bourdeauducq 2013-02-23 19:42:29 +01:00
parent 0321513726
commit ef833422c7
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
mibuild/generic_platform.py
View File

@ -197,7 +197,7 @@ class GenericPlatform:
if language is not None: if language is not None:
self.add_source(os.path.join(root, filename), language) self.add_source(os.path.join(root, filename), language)
def get_verilog(self, fragment, clock_domains=None): def get_verilog(self, fragment, clock_domains=None, **kwargs):
# We may create a temporary clock/reset generator that would request pins. # We may create a temporary clock/reset generator that would request pins.
# Save the constraint manager state so that such pin requests disappear # Save the constraint manager state so that such pin requests disappear
# at the end of this function. # at the end of this function.
@ -214,7 +214,7 @@ class GenericPlatform:
frag = fragment frag = fragment
# generate Verilog # generate Verilog
src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
clock_domains=clock_domains, return_ns=True) clock_domains=clock_domains, return_ns=True, **kwargs)
# resolve signal names in constraints # resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints() sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]