efinix: add PLL reset and locked pins

litex/build/efinix/ifacewriter.py

@@ -53,6 +53,10 @@ design.create('{2}', '{3}', './../build', overwrite=True)
         cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block['input_freq'] / 1e6)
         cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
 
+        cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
+        if block['reset'] != '':
+            cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['reset'])
+
          # Output clock 0 is enabled by default
         for i, clock in enumerate(block['clk_out']):
             if i > 0:

litex/build/efinix/platform.py

@@ -7,7 +7,7 @@
 
 import os
 
-from litex.build.generic_platform import GenericPlatform
+from litex.build.generic_platform import *
 from litex.build.efinix import common, efinity
 
 # EfinixPlatform -----------------------------------------------------------------------------------
@@ -67,3 +67,10 @@ class EfinixPlatform(GenericPlatform):
             if s == sig:
                 return resource[0]
         return None
+
+    def add_iface_io(self, name, size=1):
+        self.add_extension([(name, 0, Pins(size))])
+        tmp = self.request(name)
+        # We don't want this IO to be in the interface configuration file as a simple GPIO
+        self.toolchain.specials_gpios.append(tmp)
+        return tmp

litex/soc/cores/clock/efinix_trion.py

@@ -22,13 +22,15 @@ count = 0
 
 class TRIONPLL(Module):
     nclkouts_max = 4
-    def __init__(self, platform):
+    def __init__(self, platform, with_reset=False):
         global count
         self.logger = logging.getLogger("TRIONPLL")
         self.logger.info("Creating TRIONPLL.".format())
         self.platform   = platform
         self.nclkouts   = 0
         self.pll_name   = "pll{}".format(count)
+        self.reset      = Signal()
+        self.locked     = Signal()
 
         block = {}
         count += 1
@@ -37,6 +39,18 @@ class TRIONPLL(Module):
         block['name'] = self.pll_name
         block['clk_out'] = []
 
+        pll_locked_name = self.pll_name + '_locked'
+        block['locked'] = pll_locked_name
+        io = self.platform.add_iface_io(pll_locked_name)
+        self.comb += self.locked.eq(io)
+
+        block['reset'] = ''
+        if with_reset:
+            pll_reset_name = self.pll_name + '_reset'
+            block['reset'] = pll_reset_name
+            io = self.platform.add_iface_io(pll_reset_name)
+            self.comb += io.eq(self.reset)
+
         self.platform.toolchain.ifacewriter.blocks.append(block)
 
     def register_clkin(self, clkin, freq):
@@ -73,6 +87,9 @@ class TRIONPLL(Module):
         self.platform.add_extension([(clk_out_name, 0, Pins(1))])
         tmp = self.platform.request(clk_out_name)
 
+        if with_reset:
+            self.specials += AsyncResetSynchronizer(cd, ~self.locked)
+
         # We don't want this IO to be in the interface configuration file as a simple GPIO
         self.platform.toolchain.specials_gpios.append(tmp)
         self.comb += cd.clk.eq(tmp)