dvisampler: support differential input
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22e25347fe
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@ -19,11 +19,19 @@ class DVISampler(Module, AutoCSR):
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for datan in range(3):
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name = "data" + str(datan)
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invert = False
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try:
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s = getattr(pads, name)
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except AttributeError:
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s = getattr(pads, name + "_n")
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invert = True
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if hasattr(pads, name + "_p"):
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s = Signal()
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self.specials += Instance("IBUFDS",
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Instance.Input("I", getattr(pads, name + "_p")),
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Instance.Input("IB", getattr(pads, name + "_n")),
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Instance.Output("O", s)
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)
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else:
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try:
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s = getattr(pads, name)
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except AttributeError:
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s = getattr(pads, name + "_n")
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invert = True
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cap = DataCapture(8, invert)
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setattr(self.submodules, name + "_cap", cap)
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@ -16,6 +16,16 @@ class Clocking(Module, AutoCSR):
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###
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if hasattr(pads, "clk_p"):
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clkin = Signal()
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self.specials += Instance("IBUFDS",
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Instance.Input("I", pads.clk_p),
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Instance.Input("IB", pads.clk_n),
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Instance.Output("O", clkin)
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)
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else:
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clkin = pads.clk
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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@ -39,7 +49,7 @@ class Clocking(Module, AutoCSR):
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Instance.Output("CLKOUT3", pll_clk3),
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Instance.Output("LOCKED", pll_locked),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKIN", pads.clk),
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Instance.Input("CLKIN", clkin),
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Instance.Input("RST", self._r_pll_reset.storage)
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)
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