migen: create VerilogConvert and EDIFConvert classes and return it with convert functions

mibuild/generic_platform.py

@@ -268,17 +268,17 @@ class GenericPlatform:
 	def _get_source(self, fragment, gen_fn):
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		# generate source
+		# generate source and namespace
-		src, vns = gen_fn(fragment)
+		convert = gen_fn(fragment)
-		return src, vns
+		return str(convert), convert.ns
 
 	def get_verilog(self, fragment, **kwargs):
 		return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
-				return_ns=True, create_clock_domains=False, **kwargs))
+				create_clock_domains=False, **kwargs))
 
 	def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
 		return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
-				cell_library, vendor, device, return_ns=True, **kwargs))
+				cell_library, vendor, device, **kwargs))
 
 	def build(self, fragment):
 		raise NotImplementedError("GenericPlatform.build must be overloaded")

migen/fhdl/edif.py

@@ -182,7 +182,13 @@ def _generate_connections(f, ios, ns):
 		r[io].append(_NetBranch(portname=io, instancename=""))
 	return r
 
-def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
+class EDIFConvert:
+	def __init__(self, f, ios, cell_library, vendor, device, name="top"):
+		self.cell_library
+		self.vendor = vendor
+		self.device = device
+		self.name = name
+
 		if not isinstance(f, _Fragment):
 			f = f.get_fragment()
 		if f.comb != [] or f.sync != {}:
@@ -194,8 +200,18 @@ def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
 		instances = _generate_instances(f, ns)
 		inouts = _generate_ios(f, ios, ns)
 		connections = _generate_connections(f, ios, ns)
-	r =  _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
+
-	if return_ns:
+		self.f = f
-		return r, ns
+		self.ios = ios
-	else:
+		self.cells = cells
-		return r
+		self.ns = ns
+		self.instances = instances
+		self.inouts = inouts
+		self.connections = connections
+
+	def __str__(self):
+		return _write_edif(self.cells, self.inouts, self.instances, self.connections,
+			self.cell_library, self.name, self.device, self.vendor)
+
+def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
+	return EDIFConvert(f, ios, cell_library, vendor, device, name, return_ns)

migen/fhdl/verilog.py

@@ -266,11 +266,15 @@ def _printspecials(overrides, specials, ns):
 		r += pr
 	return r
 
-def convert(f, ios=None, name="top",
+class VerilogConvert:
-  return_ns=False,
+	def __init__(self, f, ios=None, name="top",
   			special_overrides=dict(),
   			create_clock_domains=True,
   			display_run=False):
+		self.name = name
+		self.special_overrides = special_overrides
+		self.display_run = display_run
+
 		if not isinstance(f, _Fragment):
 			f = f.get_fragment()
 		if ios is None:
@@ -297,14 +301,22 @@ def convert(f, ios=None, name="top",
 			| list_special_ios(f, True, True, True) \
 			| ios)
 
-	r = "/* Machine-generated using Migen */\n"
+		self.f = f
-	r += _printheader(f, ios, name, ns)
+		self.ios = ios
-	r += _printcomb(f, ns, display_run)
+		self.ns = ns
-	r += _printsync(f, ns)
+		self.lowered_specials = lowered_specials
-	r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
-	r += "endmodule\n"
 
-	if return_ns:
+	def __str__(self):
-		return r, ns
+		r = "/* Machine-generated using Migen */\n"
-	else:
+		r += _printheader(self.f, self.ios, self.name, self.ns)
+		r += _printcomb(self.f, self.ns, self.display_run)
+		r += _printsync(self.f, self.ns)
+		r += _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns)
+		r += "endmodule\n"
 		return r
+
+def convert(f, ios=None, name="top",
+  special_overrides=dict(),
+  create_clock_domains=True,
+  display_run=False):
+	return VerilogConvert(f, ios, name, special_overrides, create_clock_domains, display_run)

migen/sim/generic.py

@@ -87,16 +87,17 @@ class Simulator:
 		c_top = self.top_level.get(sockaddr)
 
 		fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
-		c_fragment, self.namespace = verilog.convert(fragment,
+		verilog_convert = verilog.convert(fragment,
 			ios=self.top_level.ios,
 			name=self.top_level.dut_type,
 			return_ns=True,
 			**vopts)
+		c_dut, self.namespace = str(verilog_convert), verilog_convert.ns
 
 		self.cycle_counter = -1
 
 		self.sim_runner = sim_runner
-		self.sim_runner.start(c_top, c_fragment)
+		self.sim_runner.start(c_top, c_dut)
 		self.ipc.accept()
 		reply = self.ipc.recv()
 		assert(isinstance(reply, MessageTick))