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soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor

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This commit is contained in:
Gwenhael Goavec-Merou 2023-10-30 11:13:40 +01:00
parent 9374196974
commit f06ef5205a
1 changed files with 3 additions and 3 deletions
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6
litex/soc/cores/uart.py
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@ -431,17 +431,17 @@ class Stream2Wishbone(LiteXModule):
class UARTBone(Stream2Wishbone):
def __init__(self, phy, clk_freq, cd="sys"):
def __init__(self, phy, clk_freq, cd="sys", address_width=32):
if cd == "sys":
self.phy = phy
Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq)
Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq, address_width=address_width)
else:
self.phy = ClockDomainsRenamer(cd)(phy)
self.tx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=cd)
self.rx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from=cd, cd_to="sys")
self.comb += self.phy.source.connect(self.rx_cdc.sink)
self.comb += self.tx_cdc.source.connect(self.phy.sink)
Stream2Wishbone.__init__(self, clk_freq=clk_freq)
Stream2Wishbone.__init__(self, clk_freq=clk_freq, address_width=address_width)
self.comb += self.rx_cdc.source.connect(self.sink)
self.comb += self.source.connect(self.tx_cdc.sink)