cores/cpu: rename eos-s3 to eos_s3 for compatibility

litex/soc/cores/cpu/__init__.py

@@ -136,7 +136,7 @@ CPUS = {
     "zynq7000"    : Zynq7000,
 
     # EOS-S3
-    "eos-s3"      : EOS_S3,
+    "eos_s3"      : EOS_S3,
 
     # Gowin EMCU
     'gowin_emcu'  : GowinEMCU

litex/soc/cores/cpu/eos_s3/core.py

@@ -20,8 +20,8 @@ class Open(Signal): pass
 class EOS_S3(CPU):
     variants             = ["standard"]
     family               = "arm"
-    name                 = "eos-s3"
-    human_name           = "eos-s3"
+    name                 = "eos_s3"
+    human_name           = "EOS S3"
     data_width           = 32
     endianness           = "little"
     reset_address        = 0x00000000

litex/soc/integration/soc_core.py

@@ -158,7 +158,7 @@ class SoCCore(LiteXSoC):
             integrated_rom_size = 4*len(integrated_rom_init)
 
         # Disable ROM when no CPU/hard-CPU.
-        if cpu_type in [None, "zynq7000", "eos-s3"]:
+        if cpu_type in [None, "zynq7000", "eos_s3"]:
             integrated_rom_init = []
             integrated_rom_size = 0
         self.integrated_rom_size        = integrated_rom_size