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interconnect/csr_bus: move/rewrite paged access warning.

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Was incorrectly triggered with csr_data_width=32.
This commit is contained in:
Florent Kermarrec 2020-07-06 12:26:24 +02:00
parent 9e46195299
commit f0a97791a9
1 changed files with 1 additions and 3 deletions
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4
litex/soc/interconnect/csr_bus.py
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@ -95,14 +95,12 @@ class SRAM(Module):
else:
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
mem_size = int(mem.width*mem.depth/8)
if mem_size > aligned_paging:
print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
aligned_paging, mem_size))
csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = log2_int(csrw_per_memw)
page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
printf("WARNING: SRAM CSR memory will requires paged access.")
else:
self._page = None
if read_only is None: