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gensoc: move I/O for rom initialization to make.py

This commit is contained in:
Florent Kermarrec 2015-02-27 19:40:56 +01:00
parent 074f576340
commit f1200d6388
2 changed files with 13 additions and 20 deletions
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12
make.py
View File

@ -124,7 +124,7 @@ CPU type: {}
actions["flash-bitstream"] = True actions["flash-bitstream"] = True
if not soc.with_rom: if not soc.with_rom:
actions["flash-bios"] = True actions["flash-bios"] = True
if actions["build-bitstream"] and hasattr(soc, "init_bios_memory"): if actions["build-bitstream"] and soc.with_rom:
actions["build-bios"] = True actions["build-bios"] = True
if actions["build-bios"]: if actions["build-bios"]:
actions["build-headers"] = True actions["build-headers"] = True
@ -178,7 +178,15 @@ CPU type: {}
if actions["build-bitstream"]: if actions["build-bitstream"]:
if soc.with_rom: if soc.with_rom:
soc.init_rom() with open(soc.cpu_boot_file, "rb") as boot_file:
boot_data = []
while True:
w = boot_file.read(4)
if not w:
break
boot_data.append(struct.unpack(">I", w)[0])
soc.init_rom(boot_data)
for decorator in args.decorate: for decorator in args.decorate:
soc = getattr(simplify, decorator)(soc) soc = getattr(simplify, decorator)(soc)
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option) build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)

21
misoclib/gensoc/__init__.py
View File

@ -39,7 +39,7 @@ class GenSoC(Module):
def __init__(self, platform, clk_freq, cpu_or_bridge=None, def __init__(self, platform, clk_freq, cpu_or_bridge=None,
with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000, with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
cpu_boot_file="software/bios/bios.bin", cpu_boot_file="software/bios/bios.bin",
with_rom=False, rom_size=0x8000, rom_init_now=False, with_rom=False, rom_size=0x8000,
with_sram=True, sram_size=4096, with_sram=True, sram_size=4096,
with_sdram=False, sdram_size=64*1024, with_sdram=False, sdram_size=64*1024,
with_csr=True, csr_data_width=8, csr_address_width=14, with_csr=True, csr_data_width=8, csr_address_width=14,
@ -57,7 +57,6 @@ class GenSoC(Module):
self.with_rom = with_rom self.with_rom = with_rom
self.rom_size = rom_size self.rom_size = rom_size
self.rom_init_now = rom_init_now
self.with_sram = with_sram self.with_sram = with_sram
self.sram_size = sram_size self.sram_size = sram_size
@ -93,8 +92,6 @@ class GenSoC(Module):
if with_rom: if with_rom:
self.submodules.rom = wishbone.SRAM(rom_size, read_only=True) self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
self.register_mem("rom", self.mem_map["rom"], self.rom.bus, rom_size) self.register_mem("rom", self.mem_map["rom"], self.rom.bus, rom_size)
if rom_init_now:
self.init_rom()
if with_sram: if with_sram:
self.submodules.sram = wishbone.SRAM(sram_size) self.submodules.sram = wishbone.SRAM(sram_size)
@ -118,20 +115,8 @@ class GenSoC(Module):
if with_timer: if with_timer:
self.submodules.timer0 = timer.Timer() self.submodules.timer0 = timer.Timer()
def init_rom(self, filename=None): def init_rom(self, data):
if filename is None: self.rom.mem.init = data
filename = self.cpu_boot_file
filename_ext = os.path.splitext(filename)[1]
if filename_ext != ".bin":
raise ValueError("rom_init only supports .bin files")
with open(filename, "rb") as boot_file:
boot_data = []
while True:
w = boot_file.read(4)
if not w:
break
boot_data.append(struct.unpack(">I", w)[0])
self.rom.mem.init = boot_data
def add_wb_master(self, wbm): def add_wb_master(self, wbm):
if self.finalized: if self.finalized: