mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
modify addressing (in sectors) and improve hdd model debug
This commit is contained in:
Florent Kermarrec
parent
6a783ad291
commit
f226de5ba0
5 changed files with 99 additions and 94 deletions
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@ -23,15 +23,12 @@ class SATACommandTX(Module):
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###
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sector_bits = log2_int(sector_size)
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dwords_bits = 2
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self.comb += [
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transport.sink.pm_port.eq(0),
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transport.sink.features.eq(0),
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transport.sink.lba.eq(sink.address[sector_bits-dwords_bits:]),
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transport.sink.lba.eq(sink.sector),
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transport.sink.device.eq(0xe0),
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transport.sink.count.eq(sink.length[sector_bits-dwords_bits:]),
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transport.sink.count.eq(sink.count),
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transport.sink.icc.eq(0),
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transport.sink.control.eq(0),
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]
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@ -61,11 +58,10 @@ class SATACommandTX(Module):
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["WRITE_DMA_EXT"]),
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If(transport.sink.ack,
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If(sink.stb & transport.sink.ack,
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NextState("WAIT_DMA_ACTIVATE")
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)
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)
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# XXX: split when length > 2048 dwords
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fsm.act("WAIT_DMA_ACTIVATE",
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If(from_rx.dma_activate,
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NextState("SEND_DATA")
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@ -116,7 +112,7 @@ class SATACommandTX(Module):
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]
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class SATACommandRX(Module):
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def __init__(self, transport, sector_size):
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def __init__(self, transport, sector_size, max_count):
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self.source = source = Source(command_rx_description(32))
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self.to_tx = to_tx = Source(rx_to_tx)
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self.from_tx = from_tx = Sink(tx_to_rx)
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@ -167,7 +163,7 @@ class SATACommandRX(Module):
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source.eop.eq(1),
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source.write.eq(1),
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source.success.eq(1),
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If(source.ack,
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If(source.stb & source.ack,
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NextState("IDLE")
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)
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)
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@ -207,7 +203,7 @@ class SATACommandRX(Module):
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source.read.eq(~identify),
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source.identify.eq(identify),
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source.success.eq(1),
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If(source.ack,
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If(source.stb & source.ack,
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NextState("IDLE")
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)
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)
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@ -217,9 +213,11 @@ class SATACommandRX(Module):
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]
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class SATACommand(Module):
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def __init__(self, transport, sector_size=512):
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def __init__(self, transport, sector_size=512, max_count=16):
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if max_count*sector_size > 8192:
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raise ValueError("sector_size x max_count must be <= 2048")
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self.submodules.tx = SATACommandTX(transport, sector_size)
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self.submodules.rx = SATACommandRX(transport, sector_size)
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self.submodules.rx = SATACommandRX(transport, sector_size, max_count)
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self.comb += [
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self.rx.to_tx.connect(self.tx.from_rx),
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self.tx.to_rx.connect(self.rx.from_tx)
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@ -148,8 +148,8 @@ def command_tx_description(dw):
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("write", 1),
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("read", 1),
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("identify", 1),
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("address", 32),
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("length", 32),
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("sector", 48),
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("count", 4),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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@ -13,14 +13,14 @@ from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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class CommandTXPacket(list):
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def __init__(self, write=0, read=0, identify=0, address=0, length=0, data=[]):
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def __init__(self, write=0, read=0, identify=0, sector=0, count=0, data=[]):
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self.ongoing = False
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self.done = False
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self.write = write
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self.read = read
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self.identify = identify
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self.address = address
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self.length = length
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self.sector = sector
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self.count = count
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for d in data:
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self.append(d)
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@ -47,8 +47,8 @@ class CommandStreamer(Module):
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selfp.source.write = self.packet.write
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selfp.source.read = self.packet.read
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selfp.source.identify = self.packet.identify
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selfp.source.address = self.packet.address
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selfp.source.length = self.packet.length
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selfp.source.sector = self.packet.sector
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selfp.source.count = self.packet.count
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if not self.packet.ongoing and not self.packet.done:
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selfp.source.stb = 1
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@ -105,10 +105,8 @@ class CommandLogger(Module):
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class TB(Module):
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def __init__(self):
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self.submodules.hdd = HDD(
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phy_debug=False,
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link_random_level=50, link_debug=False,
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link_debug=False, link_random_level=50,
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transport_debug=False, transport_loopback=False,
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command_debug=False,
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hdd_debug=True)
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self.submodules.link = SATALink(self.hdd.phy)
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self.submodules.transport = SATATransport(self.link)
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@ -128,12 +126,14 @@ class TB(Module):
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]
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def gen_simulation(self, selfp):
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self.hdd.allocate_mem(0x00000000, 64*1024*1024)
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write_data = [i for i in range(512//4)]
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write_packet = CommandTXPacket(write=1, address=0, length=len(write_data), data=write_data)
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hdd = self.hdd
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hdd.malloc(0, 64)
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write_data = [i for i in range(hdd.sectors2dwords(2))]
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write_len = hdd.dwords2sectors(len(write_data))
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write_packet = CommandTXPacket(write=1, sector=2, count=write_len, data=write_data)
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yield from self.streamer.send(write_packet)
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yield from self.logger.receive()
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read_packet = CommandTXPacket(read=1, address=0, length=len(write_data))
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read_packet = CommandTXPacket(read=1, sector=2, count=write_len)
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yield from self.streamer.send(read_packet)
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yield from self.logger.receive()
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read_data = self.logger.packet
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@ -144,4 +144,4 @@ class TB(Module):
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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@ -6,6 +6,13 @@ from migen.fhdl.std import *
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from lib.sata.common import *
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from lib.sata.test.common import *
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def print_with_prefix(s, prefix=""):
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if not isinstance(s, str):
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s = s.__repr__()
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s = s.split("\n")
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for l in s:
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print(prefix + l)
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# PHY Layer model
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class PHYDword:
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def __init__(self, dat=0):
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@ -49,8 +56,7 @@ class PHYSink(Module):
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self.dword.dat = selfp.sink.data
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class PHYLayer(Module):
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def __init__(self, debug=False):
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self.debug = debug
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def __init__(self):
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self.submodules.rx = PHYSink()
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self.submodules.tx = PHYSource()
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@ -63,8 +69,6 @@ class PHYLayer(Module):
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self.tx.send(packet)
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def receive(self):
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if self.debug:
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print(self)
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yield from self.rx.receive()
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def __repr__(self):
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@ -79,6 +83,9 @@ class PHYLayer(Module):
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return receiving + sending
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# Link Layer model
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def print_link(s):
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print_with_prefix(s, "[LNK]: ")
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def import_scrambler_datas():
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with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
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process.stdin.write("0x10000".encode("ASCII"))
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@ -249,6 +256,8 @@ class LinkLayer(Module):
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self.phy.send(primitives["SYNC"])
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while True:
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yield from self.phy.receive()
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if self.debug:
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print_link(self.phy)
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self.phy.send(primitives["SYNC"])
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rx_dword = self.phy.rx.dword.dat
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rx_dword = self.remove_cont(rx_dword)
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@ -264,6 +273,9 @@ class LinkLayer(Module):
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self.insert_cont()
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# Transport Layer model
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def print_transport(s):
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print_with_prefix(s, "[TRN]: ")
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def get_field_data(field, packet):
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return (packet[field.dword] >> field.offset) & (2**field.width-1)
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@ -365,7 +377,7 @@ class TransportLayer(Module):
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packet = LinkTXPacket(fis.packet)
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self.link.tx_packets.append(packet)
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if self.debug and not self.loopback:
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print(fis)
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print_transport(fis)
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def callback(self, packet):
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fis_type = packet[0] & 0xff
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@ -380,7 +392,7 @@ class TransportLayer(Module):
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else:
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fis = FIS_UNKNOWN(packet, direction="H2D")
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if self.debug:
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print(fis)
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print_transport(fis)
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if self.loopback:
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self.send(fis)
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else:
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@ -388,9 +400,8 @@ class TransportLayer(Module):
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# Command Layer model
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class CommandLayer(Module):
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def __init__(self, transport, debug=False):
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def __init__(self, transport):
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self.transport = transport
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self.debug = debug
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self.transport.set_command_callback(self.callback)
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self.hdd = None
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@ -399,103 +410,100 @@ class CommandLayer(Module):
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self.hdd = hdd
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def callback(self, fis):
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# XXX manage maximum of 2048 DWORDS per DMA
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resp = None
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if isinstance(fis, FIS_REG_H2D):
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if fis.command == regs["WRITE_DMA_EXT"]:
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resp = self.hdd.write_dma_cmd(fis)
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resp = self.hdd.write_dma_callback(fis)
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elif fis.command == regs["READ_DMA_EXT"]:
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resp = self.hdd.read_dma_cmd(fis)
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resp = self.hdd.read_dma_callback(fis)
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elif fis.command == regs["IDENTIFY_DEVICE_DMA"]:
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resp = self.hdd.identify_device_dma_cmd(fis)
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resp = self.hdd.identify_device_dma_callback(fis)
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elif isinstance(fis, FIS_DATA):
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resp = self.hdd.data_cmd(fis)
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resp = self.hdd.data_callback(fis)
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if resp is not None:
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for packet in resp:
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self.transport.send(packet)
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# HDD model
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def print_hdd(s):
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print_with_prefix(s, "[HDD]: ")
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class HDDMemRegion:
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def __init__(self, base, length):
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def __init__(self, base, count, sector_size):
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self.base = base
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self.length = length
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self.data = [0]*(length//4)
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self.count = count
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self.data = [0]*(count*sector_size//4)
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class HDD(Module):
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def __init__(self,
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phy_debug=False,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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command_debug=False,
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hdd_debug=False, hdd_sector_size=512,
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):
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###
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self.submodules.phy = PHYLayer(phy_debug)
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self.submodules.phy = PHYLayer()
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self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
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self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
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self.submodules.command = CommandLayer(self.transport, command_debug)
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self.submodules.command = CommandLayer(self.transport)
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self.command.set_hdd(self)
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self.hdd_debug = hdd_debug
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self.hdd_sector_size = hdd_sector_size
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self.debug = hdd_debug
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self.sector_size = hdd_sector_size
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self.mem = None
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self.wr_address = 0
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self.wr_length = 0
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self.wr_cnt = 0
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self.rd_address = 0
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self.rd_length = 0
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self.wr_sector = 0
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self.wr_end_sector = 0
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def allocate_mem(self, base, length):
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if self.hdd_debug:
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print("[HDD] : Allocating {n} bytes at 0x{a}".format(n=length, a=base))
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self.mem = HDDMemRegion(base, length)
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def dwords2sectors(self, n):
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return math.ceil(n*4/self.sector_size)
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def write_mem(self, adr, data):
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if self.hdd_debug:
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print("[HDD] : Writing {n} bytes at 0x{a}".format(n=len(data)*4, a=adr))
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current_adr = (adr-self.mem.base)//4
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def sectors2dwords(self, n):
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return n*self.sector_size//4
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def malloc(self, sector, count):
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if self.debug:
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s = "Allocating {n} sectors: {s} to {e}".format(n=count, s=sector, e=sector+count)
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s += " ({} KB)".format(count*self.sector_size//1024)
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print_hdd(s)
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self.mem = HDDMemRegion(sector, count, self.sector_size)
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def write(self, sector, data):
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n = math.ceil(self.dwords2sectors(len(data)))
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if self.debug:
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print_hdd("Writing sector {s} to {e}".format(s=sector, e=sector+n-1))
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for i in range(len(data)):
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self.mem.data[current_adr+i] = data[i]
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offset = self.sectors2dwords(sector)
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self.mem.data[offset+i] = data[i]
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def read_mem(self, adr, length=1):
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if self.hdd_debug:
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print("[HDD] : Reading {n} bytes at 0x{a}".format(n=length, a=adr))
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current_adr = (adr-self.mem.base)//4
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def read(self, sector, count):
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if self.debug:
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print_hdd("Reading sector {s} to {e}".format(s=sector, e=sector+count-1))
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data = []
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for i in range(length//4):
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data.append(self.mem.data[current_adr+i])
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for i in range(self.sectors2dwords(count)):
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data.append(self.mem.data[self.sectors2dwords(sector)+i])
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return data
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def write_dma_cmd(self, fis):
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self.wr_address = fis.lba_lsb
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self.wr_length = fis.count*self.hdd_sector_size
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self.wr_cnt = 0
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def write_dma_callback(self, fis):
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self.wr_sector = fis.lba_lsb + (fis.lba_msb << 32)
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self.wr_end_sector = self.wr_sector + fis.count
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return [FIS_DMA_ACTIVATE_D2H()]
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def read_dma_cmd(self, fis):
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self.rd_address = fis.lba_lsb
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self.rd_length = fis.count*self.hdd_sector_size
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self.rd_cnt = 0
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n = math.ceil(self.rd_length/(2048*4))
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packets = [FIS_REG_D2H()]
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for i in range(n):
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length = min(self.rd_length-self.rd_cnt, 2048)
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packet = self.read_mem(self.rd_address, length)
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packet.insert(0, 0)
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packets.insert(0, FIS_DATA(packet, direction="D2H"))
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return packets
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def read_dma_callback(self, fis):
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sector = fis.lba_lsb + (fis.lba_msb << 32)
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packet = self.read(sector, fis.count)
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packet.insert(0, 0)
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return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()]
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def identify_dma_cmd(self, fis):
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def identify_dma_callback(self, fis):
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packet = [i for i in range(256)]
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packet.insert(0, 0)
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return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()]
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def data_cmd(self, fis):
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self.write_mem(self.wr_address, fis.packet[1:])
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self.wr_cnt += len(fis.packet[1:])*4
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if self.wr_length == self.wr_cnt:
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def data_callback(self, fis):
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self.write(self.wr_sector, fis.packet[1:])
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self.wr_sector += self.dwords2sectors(len(fis.packet[1:]))
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if self.wr_sector == self.wr_end_sector:
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return [FIS_REG_D2H()]
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else:
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return [FIS_DMA_ACTIVATE_D2H()]
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@ -54,7 +54,7 @@ class SATATransportTX(Module):
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sink.ack.eq(1)
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)
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).Else(
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sink.ack.eq(sink.stb)
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sink.ack.eq(1)
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)
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)
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fsm.act("SEND_REG_H2D_CMD",
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@ -161,7 +161,6 @@ class SATATransportRX(Module):
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).Elif(test_type("DATA"),
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NextState("RECEIVE_DATA_CMD"),
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).Else(
|
||||
# XXX: Better to ack?
|
||||
link.source.ack.eq(1)
|
||||
)
|
||||
).Else(
|
||||
|
|
@ -180,7 +179,7 @@ class SATATransportRX(Module):
|
|||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
_decode_cmd(encoded_cmd, fis_reg_d2h_layout, source),
|
||||
If(source.ack,
|
||||
If(source.stb & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
|
@ -196,7 +195,7 @@ class SATATransportRX(Module):
|
|||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
_decode_cmd(encoded_cmd, fis_dma_activate_d2h_layout, source),
|
||||
If(source.ack,
|
||||
If(source.stb & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
|
|
|||
Loading…
Reference in a new issue