Add system Verilog support for the Vivado builder

This commit is contained in:
Martin Cornil 2019-10-10 14:06:37 +02:00
parent 37531cec81
commit f2369a4c9e
3 changed files with 13 additions and 7 deletions

View file

@ -334,7 +334,7 @@ class GenericPlatform:
for f in filenames: for f in filenames:
self.add_source(os.path.join(path, f), language, library) self.add_source(os.path.join(path, f), language, library)
def add_source_dir(self, path, recursive=True, library=None): def add_source_dir(self, path, recursive=True, language=None, library=None):
dir_files = [] dir_files = []
if recursive: if recursive:
for root, dirs, files in os.walk(path): for root, dirs, files in os.walk(path):
@ -345,9 +345,7 @@ class GenericPlatform:
if os.path.isfile(os.path.join(path, item)): if os.path.isfile(os.path.join(path, item)):
dir_files.append(os.path.join(path, item)) dir_files.append(os.path.join(path, item))
for filename in dir_files: for filename in dir_files:
language = tools.language_by_filename(filename) self.add_source(filename, language, library)
if language is not None:
self.add_source(filename, language, library)
def add_verilog_include_path(self, path): def add_verilog_include_path(self, path):
self.verilog_include_paths.add(os.path.abspath(path)) self.verilog_include_paths.add(os.path.abspath(path))

View file

@ -19,8 +19,10 @@ def language_by_filename(name):
extension = name.rsplit(".")[-1] extension = name.rsplit(".")[-1]
if extension in ["v", "vh", "vo"]: if extension in ["v", "vh", "vo"]:
return "verilog" return "verilog"
if extension in ["vhd", "vhdl", "vho"]: elif extension in ["vhd", "vhdl", "vho"]:
return "vhdl" return "vhdl"
elif extension in ["sv"]:
return "systemverilog"
return None return None

View file

@ -126,10 +126,16 @@ class XilinxVivadoToolchain:
# "-include_dirs {}" crashes Vivado 2016.4 # "-include_dirs {}" crashes Vivado 2016.4
for filename, language, library in sources: for filename, language, library in sources:
filename_tcl = "{" + filename + "}" filename_tcl = "{" + filename + "}"
tcl.append("add_files " + filename_tcl) if ("systemverilog" == language):
if language == "vhdl": tcl.append("read_verilog -sv " + filename_tcl)
elif ("verilog" == language):
tcl.append("read_verilog " + filename_tcl)
elif ("vhdl" == language):
tcl.append("read_vhdl " + filename_tcl)
tcl.append("set_property library {} [get_files {}]" tcl.append("set_property library {} [get_files {}]"
.format(library, filename_tcl)) .format(library, filename_tcl))
else:
tcl.append("add_files " + filename_tcl)
for filename in edifs: for filename in edifs:
filename_tcl = "{" + filename + "}" filename_tcl = "{" + filename + "}"
tcl.append("read_edif " + filename_tcl) tcl.append("read_edif " + filename_tcl)