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Add system Verilog support for the Vivado builder
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parent
37531cec81
commit
f2369a4c9e
3 changed files with 13 additions and 7 deletions
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@ -334,7 +334,7 @@ class GenericPlatform:
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for f in filenames:
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for f in filenames:
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self.add_source(os.path.join(path, f), language, library)
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self.add_source(os.path.join(path, f), language, library)
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def add_source_dir(self, path, recursive=True, library=None):
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def add_source_dir(self, path, recursive=True, language=None, library=None):
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dir_files = []
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dir_files = []
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if recursive:
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if recursive:
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for root, dirs, files in os.walk(path):
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for root, dirs, files in os.walk(path):
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@ -345,9 +345,7 @@ class GenericPlatform:
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if os.path.isfile(os.path.join(path, item)):
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if os.path.isfile(os.path.join(path, item)):
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dir_files.append(os.path.join(path, item))
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dir_files.append(os.path.join(path, item))
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for filename in dir_files:
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for filename in dir_files:
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language = tools.language_by_filename(filename)
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self.add_source(filename, language, library)
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if language is not None:
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self.add_source(filename, language, library)
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def add_verilog_include_path(self, path):
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def add_verilog_include_path(self, path):
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self.verilog_include_paths.add(os.path.abspath(path))
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self.verilog_include_paths.add(os.path.abspath(path))
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@ -19,8 +19,10 @@ def language_by_filename(name):
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extension = name.rsplit(".")[-1]
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extension = name.rsplit(".")[-1]
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if extension in ["v", "vh", "vo"]:
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if extension in ["v", "vh", "vo"]:
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return "verilog"
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return "verilog"
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if extension in ["vhd", "vhdl", "vho"]:
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elif extension in ["vhd", "vhdl", "vho"]:
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return "vhdl"
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return "vhdl"
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elif extension in ["sv"]:
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return "systemverilog"
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return None
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return None
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@ -126,10 +126,16 @@ class XilinxVivadoToolchain:
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# "-include_dirs {}" crashes Vivado 2016.4
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# "-include_dirs {}" crashes Vivado 2016.4
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for filename, language, library in sources:
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for filename, language, library in sources:
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filename_tcl = "{" + filename + "}"
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filename_tcl = "{" + filename + "}"
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tcl.append("add_files " + filename_tcl)
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if ("systemverilog" == language):
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if language == "vhdl":
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tcl.append("read_verilog -sv " + filename_tcl)
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elif ("verilog" == language):
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tcl.append("read_verilog " + filename_tcl)
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elif ("vhdl" == language):
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tcl.append("read_vhdl " + filename_tcl)
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tcl.append("set_property library {} [get_files {}]"
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tcl.append("set_property library {} [get_files {}]"
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.format(library, filename_tcl))
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.format(library, filename_tcl))
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else:
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tcl.append("add_files " + filename_tcl)
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for filename in edifs:
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for filename in edifs:
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filename_tcl = "{" + filename + "}"
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filename_tcl = "{" + filename + "}"
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tcl.append("read_edif " + filename_tcl)
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tcl.append("read_edif " + filename_tcl)
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