Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

mmcm: configure default divider with default_speed

Browse source
This commit is contained in:
Florent Kermarrec 2014-09-27 16:22:40 +02:00
parent 45f7f8aff5
commit f23c5aa724
3 changed files with 13 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
lib/sata/k7sataphy/__init__.py
View file

@ -9,12 +9,12 @@ from lib.sata.k7sataphy.datapath import K7SATAPHYRXAlign
from lib.sata.k7sataphy.datapath import K7SATAPHYRXConvert, K7SATAPHYTXConvert
class K7SATAPHY(Module):
def __init__(self, pads, clk_freq, host=True,):
def __init__(self, pads, clk_freq, host=True, default_speed="SATA3"):
self.sink = Sink([("d", 32)], True)
self.source = Source([("d", 32)], True)
# GTX
gtx = K7SATAPHYGTX(pads, "SATA3")
gtx = K7SATAPHYGTX(pads, default_speed)
self.comb += [
gtx.rxrate.eq(0b000),
gtx.txrate.eq(0b000),
@ -22,7 +22,7 @@ class K7SATAPHY(Module):
self.submodules += gtx
# CRG / CTRL
crg = K7SATAPHYCRG(pads, gtx, clk_freq)
crg = K7SATAPHYCRG(pads, gtx, clk_freq, default_speed)
if host:
ctrl = K7SATAPHYHostCtrl(gtx)
else:

12
lib/sata/k7sataphy/crg.py
View file

@ -25,7 +25,7 @@ class K7SATAPHYReconfig(Module):
)
class K7SATAPHYCRG(Module):
def __init__(self, pads, gtx, clk_freq):
def __init__(self, pads, gtx, clk_freq, default_speed):
self.reset = Signal()
self.ready = Signal()
@ -59,6 +59,12 @@ class K7SATAPHYCRG(Module):
mmcm_clk_i = Signal()
mmcm_clk0_o = Signal()
mmcm_clk1_o = Signal()
mmcm_div_config = {
"SATA1" : 16,
"SATA2" : 8,
"SATA3" : 4
}
mmcm_div = mmcm_div_config[default_speed]
self.specials += [
Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
Instance("MMCME2_ADV",
@ -74,10 +80,10 @@ class K7SATAPHYCRG(Module):
i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
# CLK0
p_CLKOUT0_DIVIDE_F=4.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
# CLK1
p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
p_CLKOUT1_DIVIDE=mmcm_div*2, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
),
Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
]

2
lib/sata/k7sataphy/gtx.py
View file

@ -6,7 +6,7 @@ from migen.flow.actor import Sink, Source
from lib.sata.k7sataphy.std import *
class K7SATAPHYGTX(Module):
def __init__(self, pads, default_speed="SATA3"):
def __init__(self, pads, default_speed):
self.drp = DRPBus()
# Channel - Ref Clock Ports