targets/nexys4ddr: use soc.add_ethernet method.
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@ -17,7 +17,6 @@ from litedram.modules import MT47H64M16
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from litedram.phy import s7ddrphy
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.mac import LiteEthMAC
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from litesdcard.phy import SDPHY
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from litesdcard.phy import SDPHY
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from litesdcard.clocker import SDClockerS7
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from litesdcard.clocker import SDClockerS7
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@ -55,7 +54,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
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platform = nexys4ddr.Platform()
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platform = nexys4ddr.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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# SoCSDRAM ---------------------------------------------------------------------------------
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@ -76,34 +75,12 @@ class BaseSoC(SoCSDRAM):
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geom_settings = sdram_module.geom_settings,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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timing_settings = sdram_module.timing_settings)
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def add_ethernet(self):
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# Ethernet ---------------------------------------------------------------------------------
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mem_map = {
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if with_ethernet:
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"ethmac": 0xb0000000,
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}
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mem_map.update(self.mem_map)
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# phy
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self.submodules.ethphy = LiteEthPHYRMII(
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self.submodules.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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pads = self.platform.request("eth"))
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# mac
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self.submodules.ethmac = LiteEthMAC(
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phy = self.ethphy,
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dw = 32,
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interface = "wishbone",
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endianness = self.cpu.endianness)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# timing constraints
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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def add_sdcard(self):
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def add_sdcard(self):
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sdcard_pads = self.platform.request("sdcard")
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sdcard_pads = self.platform.request("sdcard")
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@ -146,9 +123,9 @@ def main():
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help="enable SDCard support")
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help="enable SDCard support")
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args = parser.parse_args()
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
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if args.with_ethernet:
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with_ethernet=args.with_ethernet,
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soc.add_ethernet()
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**soc_sdram_argdict(args))
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if args.with_sdcard:
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if args.with_sdcard:
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soc.add_sdcard()
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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