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targets/nexys4ddr: use soc.add_ethernet method.

This commit is contained in:
Florent Kermarrec 2020-03-01 20:50:44 +01:00
parent 9735bd5bf2
commit f27225c2de
1 changed files with 10 additions and 33 deletions
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43
litex/boards/targets/nexys4ddr.py
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@ -17,7 +17,6 @@ from litedram.modules import MT47H64M16
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.mac import LiteEthMAC
from litesdcard.phy import SDPHY from litesdcard.phy import SDPHY
from litesdcard.clocker import SDClockerS7 from litesdcard.clocker import SDClockerS7
@ -55,7 +54,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = nexys4ddr.Platform() platform = nexys4ddr.Platform()
# SoCSDRAM --------------------------------------------------------------------------------- # SoCSDRAM ---------------------------------------------------------------------------------
@ -76,34 +75,12 @@ class BaseSoC(SoCSDRAM):
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
def add_ethernet(self): # Ethernet ---------------------------------------------------------------------------------
mem_map = { if with_ethernet:
"ethmac": 0xb0000000, self.submodules.ethphy = LiteEthPHYRMII(
} clock_pads = self.platform.request("eth_clocks"),
mem_map.update(self.mem_map) pads = self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# phy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
# mac
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def add_sdcard(self): def add_sdcard(self):
sdcard_pads = self.platform.request("sdcard") sdcard_pads = self.platform.request("sdcard")
@ -146,9 +123,9 @@ def main():
help="enable SDCard support") help="enable SDCard support")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
if args.with_ethernet: with_ethernet=args.with_ethernet,
soc.add_ethernet() **soc_sdram_argdict(args))
if args.with_sdcard: if args.with_sdcard:
soc.add_sdcard() soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))