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soc: Don't create a wishbone slave to LiteDRAM with no CPU 

When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-05-12 21:30:19 +10:00
parent dcc881db92
commit f28f247130
1 changed files with 3 additions and 2 deletions
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5
litex/soc/integration/soc.py
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@ -1034,7 +1034,8 @@ class LiteXSoC(SoC):
sdram_size = min(sdram_size, size) sdram_size = min(sdram_size, size)
# Add SDRAM region # Add SDRAM region
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) if self.cpu_type is not None:
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
# SoC [<--> L2 Cache] <--> LiteDRAM -------------------------------------------------------- # SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
if len(self.cpu.memory_buses): if len(self.cpu.memory_buses):
@ -1085,7 +1086,7 @@ class LiteXSoC(SoC):
# Else raise Error. # Else raise Error.
else: else:
raise NotImplementedError raise NotImplementedError
else: elif self.cpu_type is not None:
# When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM. # When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM.
# Request a LiteDRAM native port. # Request a LiteDRAM native port.