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targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection

This commit is contained in:
Florent Kermarrec 2020-01-16 13:17:33 +01:00
parent 990870d061
commit f2a1673f46
2 changed files with 10 additions and 4 deletions
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7
litex/boards/targets/arty.py
View File

@ -148,8 +148,11 @@ def main():
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = BaseSoC
cls = EtherboneSoC if args.with_etherbone else BaseSoC if args.with_ethernet:
cls = EthernetSoC
if args.with_etherbone:
cls = EtherboneSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args)) builder.build(**vivado_build_argdict(args))

7
litex/boards/targets/genesys2.py
View File

@ -139,8 +139,11 @@ def main():
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = BaseSoC
cls = EtherboneSoC if args.with_etherbone else BaseSoC if args.with_ethernet:
cls = EthernetSoC
if args.with_etherbone:
cls = EtherboneSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()