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soc/cores/jtag: Switch to stream.ClockDomainCrossing and use common_rst.

This commit is contained in:
Florent Kermarrec 2023-12-13 09:16:55 +01:00
parent 94eca8628c
commit f2c5ff376c
1 changed files with 10 additions and 6 deletions
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16
litex/soc/cores/jtag.py
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@ -448,12 +448,16 @@ class JTAGPHY(LiteXModule):
# JTAG clock domain crossing --------------------------------------------------------------- # JTAG clock domain crossing ---------------------------------------------------------------
if clock_domain != "jtag": if clock_domain != "jtag":
tx_cdc = stream.AsyncFIFO([("data", data_width)], 4) self.tx_cdc = tx_cdc = stream.ClockDomainCrossing([("data", data_width)],
tx_cdc = ClockDomainsRenamer({"write": clock_domain, "read": "jtag"})(tx_cdc) cd_from = clock_domain,
rx_cdc = stream.AsyncFIFO([("data", data_width)], 4) cd_to = "jtag",
rx_cdc = ClockDomainsRenamer({"write": "jtag", "read": clock_domain})(rx_cdc) with_common_rst = True
self.tx_cdc = tx_cdc )
self.rx_cdc = rx_cdc self.rx_cdc = rx_cdc = stream.ClockDomainCrossing([("data", data_width)],
cd_from = "jtag",
cd_to = clock_domain,
with_common_rst = True
)
self.comb += [ self.comb += [
sink.connect(tx_cdc.sink), sink.connect(tx_cdc.sink),
rx_cdc.source.connect(source) rx_cdc.source.connect(source)