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Fix base_address for LiteDRAMWishbone2Native

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Fixes `origin == None` due to https://github.com/litex-hub/litex-boards/commit/ba01776
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developandplay 2021-06-08 00:51:11 +02:00 committed by GitHub
parent a064e9d048
commit f2caeaf83a
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litex/soc/integration/soc.py
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@ -1326,7 +1326,7 @@ class LiteXSoC(SoC):
self.submodules += LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = origin)
base_address = self.bus.regions["main_ram"].origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
# Check if bus is a Native bus and connect it.
if isinstance(mem_bus, LiteDRAMNativePort):