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bus/lasmibus: bugfixes

This commit is contained in:
Sebastien Bourdeauducq 2013-06-09 23:36:32 +02:00
parent a836cba790
commit f2e2397c9d
1 changed files with 8 additions and 5 deletions
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13
migen/bus/lasmibus.py
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@ -50,7 +50,6 @@ class Crossbar(Module):
controller_bits = log2_int(ncontrollers, False) controller_bits = log2_int(ncontrollers, False)
self.masters = [Interface(rca_bits + bank_bits + controller_bits, dw, 1, read_latency, write_latency) self.masters = [Interface(rca_bits + bank_bits + controller_bits, dw, 1, read_latency, write_latency)
for i in range(nmasters)] for i in range(nmasters)]
masters_a = Array(self.masters)
### ###
@ -61,6 +60,7 @@ class Crossbar(Module):
controller_selected = [ca == nc for ca in m_ca] controller_selected = [ca == nc for ca in m_ca]
else: else:
controller_selected = [1]*nmasters controller_selected = [1]*nmasters
master_acks = [0]*nmasters
for nb in range(nbanks): for nb in range(nbanks):
bank = getattr(controller, "bank"+str(nb)) bank = getattr(controller, "bank"+str(nb))
@ -77,10 +77,13 @@ class Crossbar(Module):
# route requests # route requests
self.comb += [ self.comb += [
bank.adr.eq(Array(m_rca)[rr.grant]), bank.adr.eq(Array(m_rca)[rr.grant]),
bank.we.eq(masters_a[rr.grant].we), bank.we.eq(Array(self.masters)[rr.grant].we),
bank.stb.eq(masters_a[rr.grant].stb), bank.stb.eq(Array(bank_requested)[rr.grant])
masters_a[rr.grant].ack.eq(bank.ack)
] ]
master_acks = [master_ack | ((rr.grant == nm) & bank.ack)
for nm, master_ack in enumerate(master_acks)]
self.comb += [master.ack.eq(master_ack) for master, master_ack in zip(self.masters, master_acks)]
# route data writes # route data writes
controller_selected_wl = controller_selected controller_selected_wl = controller_selected
@ -215,7 +218,7 @@ class Target(Module):
self.model = model self.model = model
self.bus = Interface(*ifargs, **ifkwargs) self.bus = Interface(*ifargs, **ifkwargs)
self.rd_pipeline = [None]*self.bus.read_latency self.rd_pipeline = [None]*self.bus.read_latency
self.wr_pipeline = [None]*self.bus.write_latency self.wr_pipeline = [None]*(self.bus.write_latency + 1)
def do_simulation(self, s): def do_simulation(self, s):
# determine banks with pending requests # determine banks with pending requests