soc/cores/timer: fix typo (thanks xobs)

This commit is contained in:
Florent Kermarrec 2019-09-18 10:45:38 +02:00
parent 28885064f7
commit f2e84a5800
1 changed files with 1 additions and 1 deletions

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@ -19,7 +19,7 @@ class Timer(Module, AutoCSR):
self._reload = CSRStorage(width, description=
"""Reload value when timer reaches 0.
This register is used to create a Periodic timer and specify the timer's period in clock
cycles. For a One-Shot timer, this register need to be set to 0.""")
cycles. For a One-Shot timer, this register needs to be set to 0.""")
self._en = CSRStorage(1, description=
"""Enable. Write 1 to enable/start the timer, 0 to disable the timer""")
self._update_value = CSRStorage(1, description=